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1. 发明授权

US08681026B2 Digital to analog converter 有权
标题翻译：数模转换器
公开(公告)号：US08681026B2
公开(公告)日：2014-03-25
申请号：US13408173
申请日：2012-02-29
申请人： Jinwen Xiao , Pavel Konecny , Axel Thomsen , Ka Y. Leung
发明人： Jinwen Xiao , Pavel Konecny , Axel Thomsen , Ka Y. Leung
IPC分类号： H03M1/06
CPC分类号： H03M1/1047 , H03M1/745 , H03M1/785
摘要： An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.
摘要翻译：使用主数模转换器（DAC）和子DAC将输入数字信号转换为模拟信号。从输入数字信号中减去偏移值，以生成偏移调整数字信号。主DAC将偏移调整后的数字信号转换为第一个模拟信号。基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。子DAC将第二数字转换为第二模拟信号，当与第一模拟信号组合时，该模拟信号提供输入数字信号的模拟表示。

2. 发明申请

US20130222162A1 DIGITAL TO ANALOG CONVERTER 有权
标题翻译：数字到模拟转换器
公开(公告)号：US20130222162A1
公开(公告)日：2013-08-29
申请号：US13408173
申请日：2012-02-29
申请人： Jinwen Xiao , Pavel Konecny , Axel Thomsen , Ka Y. Leung
发明人： Jinwen Xiao , Pavel Konecny , Axel Thomsen , Ka Y. Leung
IPC分类号： H03M1/10 , H03M1/66
CPC分类号： H03M1/1047 , H03M1/745 , H03M1/785
摘要： An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.
摘要翻译：使用主数模转换器（DAC）和子DAC将输入数字信号转换为模拟信号。从输入数字信号中减去偏移值，以生成偏移调整数字信号。主DAC将偏移调整后的数字信号转换为第一个模拟信号。基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。子DAC将第二数字转换为第二模拟信号，当与第一模拟信号组合时，其提供输入数字信号的模拟表示。

3. 发明授权

US08803360B2 Boot-strap regulator for gate driver 有权
标题翻译：门驱动器的引导调节器
公开(公告)号：US08803360B2
公开(公告)日：2014-08-12
申请号：US13076333
申请日：2011-03-30
申请人： Pavel Konecny , Jinwen Xiao
发明人： Pavel Konecny , Jinwen Xiao
IPC分类号： H02J1/10
CPC分类号： H03F3/217 , Y10T307/50
摘要： Techniques are disclosed relating to supplying a power supply voltage to a gate driver. In one embodiment, an apparatus is disclosed that includes a first transistor configured to raise a voltage at a node and a second transistor configured to lower the voltage at the node. The apparatus further includes a first driver configured to receive a first power supply voltage, and to use the first power supply voltage to control a gate voltage of the first transistor. The apparatus further includes a second driver configured to receive a second power supply voltage, and to use the second power supply voltage to control a gate voltage of the second transistor. In such an embodiment, the apparatus includes a first regulator coupled to the first driver and configured to generate the first power supply voltage based on the second power supply voltage.
摘要翻译：公开了关于向栅极驱动器提供电源电压的技术。在一个实施例中，公开了一种装置，其包括被配置为升高节点处的电压的第一晶体管和被配置为降低节点处的电压的第二晶体管。该装置还包括被配置为接收第一电源电压的第一驱动器，以及使用第一电源电压来控制第一晶体管的栅极电压。该装置还包括被配置为接收第二电源电压的第二驱动器，并且使用第二电源电压来控制第二晶体管的栅极电压。在这种实施例中，该装置包括耦合到第一驱动器并被配置为基于第二电源电压产生第一电源电压的第一调节器。

4. 发明授权

US08508298B2 Amplifier using master-slave control scheme 有权
标题翻译：放大器采用主从控制方案
公开(公告)号：US08508298B2
公开(公告)日：2013-08-13
申请号：US13045279
申请日：2011-03-10
申请人： Pavel Konecny , Jinwen Xiao
发明人： Pavel Konecny , Jinwen Xiao
IPC分类号： H03F3/217
CPC分类号： H03F3/2173
摘要： Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received.
摘要翻译：公开了关于晶体管的充电和放电门的技术。在一个实施例中，装置包括第一和第二驱动器。第一驱动器被配置为对第一晶体管的栅极进行放电，并响应于达到第一晶体管的米勒平台，向第二驱动器发送电荷指示。第二驱动器被配置为响应于接收到充电指示而将第二晶体管的栅极充电到高于阈值电压。在一些实施例中，第二驱动器被配置为当第一驱动器开始放电第一晶体管的栅极开始时开始将第二晶体管的栅极充电到低于阈值电压的电压，并等待对第二晶体管的栅极充电高于阈值电压，直到收到充电指示为止。

5. 发明申请

US20120249099A1 BOOT-STRAP REGULATOR FOR GATE DRIVER 有权
标题翻译：门控驱动器的引导调节器
公开(公告)号：US20120249099A1
公开(公告)日：2012-10-04
申请号：US13076333
申请日：2011-03-30
申请人： Pavel Konecny , Jinwen Xiao
发明人： Pavel Konecny , Jinwen Xiao
IPC分类号： G05F1/10
CPC分类号： H03F3/217 , Y10T307/50
摘要： Techniques are disclosed relating to supplying a power supply voltage to a gate driver. In one embodiment, an apparatus is disclosed that includes a first transistor configured to raise a voltage at a node and a second transistor configured to lower the voltage at the node. The apparatus further includes a first driver configured to receive a first power supply voltage, and to use the first power supply voltage to control a gate voltage of the first transistor. The apparatus further includes a second driver configured to receive a second power supply voltage, and to use the second power supply voltage to control a gate voltage of the second transistor. In such an embodiment, the apparatus includes a first regulator coupled to the first driver and configured to generate the first power supply voltage based on the second power supply voltage.
摘要翻译：公开了关于向栅极驱动器提供电源电压的技术。在一个实施例中，公开了一种装置，其包括被配置为升高节点处的电压的第一晶体管和被配置为降低节点处的电压的第二晶体管。该装置还包括被配置为接收第一电源电压的第一驱动器，以及使用第一电源电压来控制第一晶体管的栅极电压。该装置还包括被配置为接收第二电源电压的第二驱动器，并且使用第二电源电压来控制第二晶体管的栅极电压。在这种实施例中，该装置包括耦合到第一驱动器并被配置为基于第二电源电压产生第一电源电压的第一调节器。

6. 发明申请

US20120229211A1 AMPLIFIER USING FAST DISCHARGING REFERENCE 有权
标题翻译：放大器使用快速放大参考
公开(公告)号：US20120229211A1
公开(公告)日：2012-09-13
申请号：US13045233
申请日：2011-03-10
申请人： Pavel Konecny , Jinwen Xiao , John M. Khoury
发明人： Pavel Konecny , Jinwen Xiao , John M. Khoury
IPC分类号： H03F3/217 , H03K3/00
CPC分类号： H03K7/08 , H03F3/2173 , H03K17/166 , H03K2217/0027 , H03K2217/0045
摘要： Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.
摘要翻译：公开了关于对晶体管的栅极进行充电和放电的技术。在一个实施例中，公开了一种装置，其包括被配置为对晶体管的栅极进行放电的驱动器。驱动器被配置为以第一速率排放门，直到达到晶体管的Miller平台，并且在达到Miller平台之后以第二速率排出门。在这种实施例中，第一速率大于第二速率。在一些实施例中，驱动器还被配置为以三速对晶体管的栅极充电，直到达到晶体管的Miller平台为止，并且在达到Miller平台之后以第四速率对栅极充电，第三速率大于第四率。在一些实施例中，该装置是D类放大器。

7. 发明申请

US20120229212A1 AMPLIFIER USING MASTER-SLAVE CONTROL SCHEME 有权
标题翻译：使用主从控制方案的放大器
公开(公告)号：US20120229212A1
公开(公告)日：2012-09-13
申请号：US13045279
申请日：2011-03-10
申请人： Pavel Konecny , Jinwen Xiao
发明人： Pavel Konecny , Jinwen Xiao
IPC分类号： H03F3/217 , H03B5/02
CPC分类号： H03F3/2173
摘要： Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received.
摘要翻译：公开了关于晶体管的充电和放电门的技术。在一个实施例中，装置包括第一和第二驱动器。第一驱动器被配置为对第一晶体管的栅极进行放电，并响应于达到第一晶体管的米勒平台，向第二驱动器发送电荷指示。第二驱动器被配置为响应于接收到充电指示而将第二晶体管的栅极充电到高于阈值电压。在一些实施例中，第二驱动器被配置为当第一驱动器开始放电第一晶体管的栅极开始时开始将第二晶体管的栅极充电到低于阈值电压的电压，并等待对第二晶体管的栅极充电高于阈值电压，直到收到充电指示为止。

8. 发明授权

US08493146B2 Amplifier using fast discharging reference 有权
标题翻译：放大器采用快速放电参考
公开(公告)号：US08493146B2
公开(公告)日：2013-07-23
申请号：US13045233
申请日：2011-03-10
申请人： Pavel Konecny , Jinwen Xiao , John M. Khoury
发明人： Pavel Konecny , Jinwen Xiao , John M. Khoury
IPC分类号： H03F3/217
CPC分类号： H03K7/08 , H03F3/2173 , H03K17/166 , H03K2217/0027 , H03K2217/0045
摘要： Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.
摘要翻译：公开了关于对晶体管的栅极进行充电和放电的技术。在一个实施例中，公开了一种装置，其包括被配置为对晶体管的栅极进行放电的驱动器。驱动器被配置为以第一速率排放门，直到达到晶体管的Miller平台，并且在达到Miller平台之后以第二速率排出门。在这种实施例中，第一速率大于第二速率。在一些实施例中，驱动器还被配置为以三速对晶体管的栅极充电，直到达到晶体管的Miller平台为止，并且在达到Miller平台之后以第四速率对栅极充电，第三速率大于第四率。在一些实施例中，该装置是D类放大器。

9. 发明申请

US20140176250A1 Relaxation Oscillator 有权
标题翻译：放松振荡器
公开(公告)号：US20140176250A1
公开(公告)日：2014-06-26
申请号：US13721885
申请日：2012-12-20
申请人： Axel Thomsen , Pavel Konecny , Xiaodong Wang
发明人： Axel Thomsen , Pavel Konecny , Xiaodong Wang
IPC分类号： H03K3/011
CPC分类号： H03K3/0231
摘要： In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.
摘要翻译：在一个实施例中，一种方法包括：在由振荡器产生的时钟信号的周期的第一部分期间，对第一开关电容器级的第一电容器进行预充电，直到第一比较器确定第一开关的第一节点电压电容器级大于第一参考电压节点处的第一参考电压; 将第二参考电压施加到所述第一参考电压节点; 并且响应于所述时钟信号的第一边沿，对所述第一电容器充电直到所述第一比较器确定所述第一节点电压大于所述第一参考电压节点处的所述第二参考电压。

10. 发明授权

US09099994B2 Relaxation oscillator 有权
标题翻译：放松振荡器
公开(公告)号：US09099994B2
公开(公告)日：2015-08-04
申请号：US13721885
申请日：2012-12-20
申请人： Axel Thomsen , Pavel Konecny , Xiaodong Wang
发明人： Axel Thomsen , Pavel Konecny , Xiaodong Wang
IPC分类号： H03K3/011 , H03K3/0231
CPC分类号： H03K3/0231
摘要： In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.
摘要翻译：在一个实施例中，一种方法包括：在由振荡器产生的时钟信号的周期的第一部分期间，对第一开关电容器级的第一电容器进行预充电，直到第一比较器确定第一开关的第一节点电压电容器级大于第一参考电压节点处的第一参考电压; 将第二参考电压施加到所述第一参考电压节点; 并且响应于所述时钟信号的第一边缘，对所述第一电容器充电直到所述第一比较器确定所述第一节点电压大于所述第一参考电压节点处的所述第二参考电压。

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