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31. 发明授权

US08754719B1 Integrated circuit devices using analog dividers 有权
标题翻译：使用模拟分频器的集成电路器件
公开(公告)号：US08754719B1
公开(公告)日：2014-06-17
申请号：US13334535
申请日：2011-12-22
申请人： Justin O'Day
发明人： Justin O'Day
IPC分类号： H03B5/08
CPC分类号： H03B19/14 , H03K5/086 , H03K23/50
摘要： A divider for use in an integrated circuit chip, such as a clock generator chip, includes a ramp generator circuit configured to generate a ramp signal and a synchronous detector circuit configured to receive the ramp signal and an input clock signal and to responsively control the ramp signal generator circuit to generate an output clock signal at an output of the synchronous detector circuit. In some embodiments, the synchronous detector circuit may include a voltage threshold detector circuit configured to receive the ramp signal and to generate a detection signal responsive thereto and a synchronous latch circuit having a clock input configured to receive the input clock signal and a data input configured to receive the detection signal. The synchronous latch circuit may be configured to control the ramp generator circuit.
摘要翻译：用于诸如时钟发生器芯片的集成电路芯片中的分压器包括：斜坡发生器电路，其被配置为产生斜坡信号;以及同步检测器电路，其被配置为接收斜坡信号和输入时钟信号，并且响应地控制斜坡信号发生器电路，以在同步检测器电路的输出端产生输出时钟信号。在一些实施例中，同步检测器电路可以包括电压阈值检测器电路，其被配置为接收斜坡信号并响应于此产生检测信号;以及同步锁存电路，具有配置成接收输入时钟信号的时钟输入和配置的数据输入以接收检测信号。同步锁存电路可以被配置为控制斜坡发生器电路。

32. 发明授权

US08754673B1 Adaptive reference voltage generators that support high speed signal detection 有权
标题翻译：支持高速信号检测的自适应参考电压发生器
公开(公告)号：US08754673B1
公开(公告)日：2014-06-17
申请号：US13936900
申请日：2013-07-08
申请人： Integrated Device Technology, Inc.
发明人： Wei Wang , Yumin Zhang
IPC分类号： H03K5/22
CPC分类号： H03K5/2481
摘要： An integrated circuit device includes a reference voltage generator, which is configured to generate an adaptive reference voltage (Vref) that varies inversely relative to changes in magnitude of a data signal (DATA) received at an input thereof. This reference voltage generator includes a totem pole arrangement of at least two variable impedance elements having control terminals capacitively coupled (by respective capacitors) to the input. A current mirror is electrically coupled to the totem pole arrangement of at least two variable impedance elements. A comparator is also included. The comparator has a first input terminal that receives the adaptive reference voltage and a second input terminal that receives the data signal.
摘要翻译：集成电路装置包括参考电压发生器，其被配置为产生相对于在其输入处接收的数据信号（DATA）的幅度变化而相反变化的自适应参考电压（Vref）。该参考电压发生器包括具有至少两个可变阻抗元件的图腾柱布置，该可变阻抗元件具有与输入电容耦合（通过相应的电容器）的控制端。电流镜电耦合到至少两个可变阻抗元件的图腾柱布置。还包括一个比较器。比较器具有接收自适应参考电压的第一输入端子和接收数据信号的第二输入端子。

33. 发明授权

US08633635B1 Microelectromechanical resonators with thermally-actuated frequency tuning beams 有权
标题翻译：具有热驱动频率调谐波束的微机电谐振器
公开(公告)号：US08633635B1
公开(公告)日：2014-01-21
申请号：US13174082
申请日：2011-06-30
申请人： Wanling Pan
发明人： Wanling Pan
IPC分类号： H03H3/04
CPC分类号： H03H9/2405 , H03H2009/02165 , H03H2009/02496 , H03H2009/241
摘要： A microelectromechanical resonator includes a resonator body anchored to a substrate by at least a pair of tethers that suspend the resonator body opposite an underlying opening in the substrate. A first thermally-actuated tuning beam is provided, which is mechanically coupled to a first portion of the resonator body that is spaced apart from the pair of tethers. The first thermally-actuated tuning beam is configured to induce a mechanical stress in the resonator body by establishing a thermal expansion difference between the first thermally-actuated tuning beam and the resonator body in response to a passing of current through the first thermally-actuated tuning beam.
摘要翻译：微机电谐振器包括通过至少一对将谐振器体悬挂在衬底中的下面开口相对的系绳的方式锚固到衬底的谐振器体。提供了第一热致动调谐光束，其被机械耦合到与所述一对系绳间隔开的谐振器本体的第一部分。第一热致动调谐波束被配置为通过响应于通过第一热驱动调谐器的电流而在第一热致动调谐波束和谐振器本体之间建立热膨胀差而在谐振器本体中引起机械应力光束。

34. 发明授权

US08604848B1 MEMS-based frequency synthesizers having variable bandwidth temperature compensation 失效
标题翻译：具有可变带宽温度补偿的基于MEMS的频率合成器
公开(公告)号：US08604848B1
公开(公告)日：2013-12-10
申请号：US13538719
申请日：2012-06-29
申请人： Chien Chen Chen , Pavan Kumar Alli , Yongchou Lo , Minhui Yan , YuanHeng Lo , Harmeet Bhugra
发明人： Chien Chen Chen , Pavan Kumar Alli , Yongchou Lo , Minhui Yan , YuanHeng Lo , Harmeet Bhugra
IPC分类号： H03L7/06
CPC分类号： H03L7/1974 , H03L1/022 , H03L7/104
摘要： A frequency synthesizer includes a frequency generator configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent code. A temperature sensor is provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent code in response to the temperature measurement signal and a plurality of clocks having unequal frequencies. The control circuit can include a cascaded arrangement of an oversampled data converter and a digital filter, which are sequentially responsive to first and second ones of the plurality of clocks during generation of the periodic output signal by the frequency generator.
摘要翻译：频率合成器包括：频率发生器，被配置为响应于周期性输入信号和与温度相关的代码产生周期性输出信号。提供了温度传感器，其被配置为响应于检测到频率合成器的至少一部分的温度而产生温度测量信号。提供控制电路，其被配置为响应于温度测量信号和具有不等频率的多个时钟产生温度相关代码。控制电路可以包括过采样数据转换器和数字滤波器的级联布置，其在由频率发生器产生周期性输出信号期间顺序响应多个时钟中的第一和第二时钟。

35. 发明授权

US08542040B1 Reconfigurable divider circuits with hybrid structure 有权
标题翻译：具有混合结构的可重构分频电路
公开(公告)号：US08542040B1
公开(公告)日：2013-09-24
申请号：US13285103
申请日：2011-10-31
申请人： Justin O'Day
发明人： Justin O'Day
IPC分类号： H03B19/00
CPC分类号： H03K23/00 , H03K23/667
摘要： An integrated circuit includes a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal and a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal. The integrated circuit further includes a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.
摘要翻译：集成电路包括：第一可变分频器电路，被配置为接收时钟信号并且响应于第一控制输入而施加较低范围的整数分频因子以产生第一分频时钟信号;以及第二可变分频器电路，被配置为接收时钟信号并且响应于第二控制输入施加整数除数因子的上限范围以产生第二分频时钟信号。集成电路还包括复用器电路，其被配置为响应于第三控制输入选择性地传递第一和第二分频时钟信号。

36. 发明授权

US08368487B1 Thin-film bulk acoustic resonators having multi-axis acoustic wave propagation therein 有权
标题翻译：具有多轴声波传播的薄膜体声共振器
公开(公告)号：US08368487B1
公开(公告)日：2013-02-05
申请号：US12713940
申请日：2010-02-26
申请人： Logan D. Sorenson
发明人： Logan D. Sorenson
IPC分类号： H03H9/15 , H03H9/13 , H03H9/54
CPC分类号： H03H9/17 , H03H2009/155 , H03H2009/241
摘要： Microelectromechanical resonators include a resonator body anchored to a surrounding substrate by at least one support that holds the resonator body opposite a recess in the substrate. The resonator body has first and second pluralities of interdigitated drive and sense electrodes thereon. The first plurality of interdigitated drive and second electrodes are aligned to a first axis of acoustic wave propagation in the resonator body when the resonator body is operating at resonance. In contrast, the second plurality of interdigitated drive and sense electrodes are aligned to a second axis of acoustic wave propagation in the resonator body. This second axis of acoustic wave propagation preferably extends at an angle in a range from 60° to 120° relative to the first axis and, more preferably, at an angle of 90° relative to the first axis. The resonator body may also be configured to have a first side that is oriented at a 45° angle relative to the first axis of acoustic wave propagation and oriented at a 45° angle relative to the second axis of acoustic wave propagation.
摘要翻译：微机电谐振器包括通过将谐振器本体保持在衬底相对的凹部的至少一个支撑件固定到周围衬底的谐振器体。谐振器体在其上具有第一和第二多个交错的驱动和感测电极。当谐振器本体在谐振操作时，第一组多个交叉驱动和第二电极与谐振器体中的声波传播的第一轴对准。相比之下，第二多个叉指驱动和感测电极与谐振器主体中的声波传播的第二轴对准。声波传播的第二轴优选相对于第一轴线以60°至120°的角度延伸，更优选地相对于第一轴线以90°的角度延伸。谐振器主体还可以被配置为具有相对于声波传播的第一轴成45°角定向的第一侧，并相对于声波传播的第二轴成45°角定向。

37. 发明授权

US08283256B1 Methods of forming microdevice substrates using double-sided alignment techniques 有权
标题翻译：使用双面对准技术形成微装置基板的方法
公开(公告)号：US08283256B1
公开(公告)日：2012-10-09
申请号：US13034004
申请日：2011-02-24
申请人： Wanling Pan , Harmeet Bhugra
发明人： Wanling Pan , Harmeet Bhugra
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： B81C1/00603
摘要： Methods of forming substrates having two-sided microstructures therein include selectively etching a first surface of the substrate to define a plurality of alignment keys therein that extend through the substrate to a second surface thereof. A direct photolithographic alignment step is then performed on a second surface of the substrate by aligning a photolithography mask to the plurality of alignment keys at the second surface. This direct alignment step is performed during steps to photolithographically define patterns in the second surface.
摘要翻译：在其中形成具有双面微结构的衬底的方法包括选择性地蚀刻衬底的第一表面以在其中限定其中延伸穿过衬底到其第二表面的多个对准键。然后通过将光刻掩模与第二表面上的多个对准键对准，在衬底的第二表面上执行直接光刻对准步骤。在步骤中执行该直接对准步骤以光刻地限定第二表面中的图案。

38. 发明授权

US08093958B2 Clock, frequency reference, and other reference signal generator with a controlled quality factor 有权
标题翻译：时钟，频率参考和其他具有受控质量因素的参考信号发生器
公开(公告)号：US08093958B2
公开(公告)日：2012-01-10
申请号：US12013440
申请日：2008-01-12
申请人： Justin O'Day , Michael Shannon McCorquodale , Scott Michael Pernia , Nam Duc Nguyen , Ralph Beaudouin , Sundus Kubba
发明人： Justin O'Day , Michael Shannon McCorquodale , Scott Michael Pernia , Nam Duc Nguyen , Ralph Beaudouin , Sundus Kubba
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1253 , H03B5/1265 , H03B5/1287 , H03B5/1293 , H03L1/02 , H03L7/08
摘要： Exemplary embodiments of the invention provide a reference signal generator having a controlled quality (“Q”) factor. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, which generates a first reference signal having a resonant frequency, and a plurality of reactance modules couplable to the reference resonator. Each reactance module comprises one or more reactance unit cells, and each reactance unit cell comprises a reactance element coupled in series to a switching element. In exemplary embodiments, the reactance element is a capacitor having a predetermined unit of capacitance, and the switching element is a transistor having a predetermined resistance when in an off state. The ratio of capacitance to resistance is substantially constant for all reactance modules of the plurality of reactance modules.
摘要翻译：本发明的示例性实施例提供具有受控质量（“Q”）因子的参考信号发生器。产生谐波参考信号的示例性装置包括产生具有共振频率的第一参考信号的参考谐振器，例如LC槽，以及可耦合到参考谐振器的多个电抗模块。每个电抗模块包括一个或多个电抗单位电池，并且每个电抗单元包括与开关元件串联耦合的电抗元件。在示例性实施例中，电抗元件是具有预定电容单位的电容器，并且当处于断开状态时，开关元件是具有预定电阻的晶体管。对于多个电抗模块的所有电抗模块，电容与电阻的比率基本上是恒定的。

39. 发明授权

US07882280B2 Packet processing switch and methods of operation thereof 有权
标题翻译：分组处理开关及其操作方法
公开(公告)号：US07882280B2
公开(公告)日：2011-02-01
申请号：US11395575
申请日：2006-03-31
申请人： Bertan Tezcan , William Terry Beane , Scott Darnell
发明人： Bertan Tezcan , William Terry Beane , Scott Darnell
IPC分类号： G06F3/00 , G06F11/00
CPC分类号： H04L49/30 , H04L45/52 , H04L47/70 , H04L49/10 , H04L49/109 , H04L49/1546 , H04L49/251 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3063 , H04L49/35
摘要： A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.
摘要翻译：分组交换集成电路芯片被配置为从多个外部源接收诸如RapidIO TM兼容分组的分组，并且将所接收的分组中的数据选择性地传递到多个外部接收者。芯片被配置为不修改地传递第一接收到的分组，并且终止第二接收分组并且预处理其有效载荷以产生新的分组。芯片可以被配置为对第二接收分组执行信号采样处理操作，例如比特扩展，比特截断，比特重排序和/或比特算术运算。芯片还可以被配置为基于接收到的分组中的目的地地址管理第一和第二接收分组。

40. 发明授权

US07842613B1 Methods of forming microelectronic packaging substrates having through-substrate vias therein 有权
标题翻译：形成其中具有贯通基板通孔的微电子封装基板的方法
公开(公告)号：US07842613B1
公开(公告)日：2010-11-30
申请号：US12349677
申请日：2009-01-07
申请人： Kuolung Lei
发明人： Kuolung Lei
IPC分类号： H01L21/44
CPC分类号： B81C1/00301 , H01L21/4846 , H01L23/49805 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a substrate for microelectronic packaging may include electroplating a metal seed layer onto a sidewall of a trench extending through the substrate. The sidewall may be patterned to have at least one slot therein that extends through the substrate. This slot is formed to be sufficiently narrow to block plating of the metal seed layer onto sidewalls of the slot. Thereafter, the at least a pair of electrodes are selectively electroplated onto side-by-side portions of the metal seed layer on the sidewall of the trench. During this electroplating step, the slot is used to provide a self-aligned separation between the pair of electrodes.
摘要翻译：形成用于微电子封装的衬底的方法可以包括将金属种子层电镀到延伸穿过衬底的沟槽的侧壁上。侧壁可以被图案化以在其中具有延伸穿过基底的至少一个狭槽。该槽形成为足够窄以阻挡金属种子层在槽的侧壁上的电镀。此后，至少一对电极选择性地电镀在沟槽的侧壁上的金属种子层的并排部分上。在该电镀步骤期间，槽用于在一对电极之间提供自对准的间隔。

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