专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5727193A Clock signal and line voltage control for efficient power consumption 失效
标题翻译：时钟信号和线路电压控制，实现高效能耗
公开(公告)号：US5727193A
公开(公告)日：1998-03-10
申请号：US444268
申请日：1995-05-18
申请人： Kesatoshi Takeuchi
发明人： Kesatoshi Takeuchi
IPC分类号： G06F1/04 , G06F1/08 , G06F1/32 , G06F15/78
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02B60/1217 , Y02B60/1282 , Y02B60/1285
摘要： A frequency of an operation clock signal CPCK output from a PLL circuit 3 is determined with division factors N and M stored in division factor memories 2 and 12. A voltage control signal LPS is input into a voltage-controlled oscillator in the PLL circuit 3 as well as to a line voltage control circuit 9. The line voltage control circuit 9 controls the level of a line voltage E supplied to other circuits including a CPU 1, in response to the voltage control signal LPS. Efficient power consumption and an appropriate operation speed are simultaneously attained because both of the frequency of the operation clock signal CPCK and the level of the line voltage E depend upon the voltage level of the voltage control signal LPS.
摘要翻译：由分配因子存储器2和12中存储的分频因子N和M确定从PLL电路3输出的操作时钟信号CPCK的频率。电压控制信号LPS被输入到PLL电路3中的压控振荡器中，如以及线路电压控制电路9.线路电压控制电路9响应于电压控制信号LPS来控制提供给包括CPU 1的其他电路的线路电压E的电平。由于操作时钟信号CPCK的频率和线路电压E的电平都取决于电压控制信号LPS的电压电平，因此同时实现高效的功耗和合适的操作速度。

22. 发明授权

US5655127A Method and apparatus for control of power consumption in a computer system 失效
标题翻译：用于控制计算机系统中功耗的方法和装置
公开(公告)号：US5655127A
公开(公告)日：1997-08-05
申请号：US612673
申请日：1996-03-08
申请人： Jeffrey L. Rabe , Zohar Bogin , Ajay V. Bhatt , James P. Kardach , Nilesh V. Shah
发明人： Jeffrey L. Rabe , Zohar Bogin , Ajay V. Bhatt , James P. Kardach , Nilesh V. Shah
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/3287 , Y02B60/1282 , Y02B60/32
摘要： A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.
摘要翻译：一种具有响应低功率模式和全功率工作模式的计算机系统。计算机系统包括功率消耗控制器，处理器和通信设备。功率消耗控制器响应于低功率事件或完全运行的事件而产生中断信号。功耗控制器还产生时钟控制信号。时钟控制信号在全功率工作模式期间被断言，并且在低功率操作模式期间另行断言第一持续时间并且断言第二持续时间。响应于断言的时钟控制信号，处理器将内部时钟信号抑制到处理器内的至少一个功能块，并且响应于无效时钟控制信号，处理器将内部时钟信号发送到内部时钟信号中的至少一个功能块处理器。通过在低功率操作模式期间将内部时钟信号发送到处理器内的至少一个功能块，处理器可以在低功率操作模式期间响应来自通信设备的通信信号。

23. 发明授权

US5586332A Power management for low power processors through the use of auto clock-throttling 失效
标题翻译：通过使用自动时钟调节功能管理低功耗处理器
公开(公告)号：US5586332A
公开(公告)日：1996-12-17
申请号：US036343
申请日：1993-03-24
申请人： Sanjay Jain , Deepak J. Aatresh
发明人： Sanjay Jain , Deepak J. Aatresh
IPC分类号： G06F1/32
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30083 , G06F9/3869 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： A clock throttling mechanism turns off certain processor components to minimize power consumption. The processor detects the issuance of certain bus cycles or the execution of certain instructions which typically cause the processor to be idle for a period of time. Control circuitry detects the existence of the instruction and/or bus cycle and shuts down the clock driving certain processor components during that idle period. The control circuitry then detects the occurrence or upcoming occurrence of an event to which the processor responds and becomes active. At detection of this event, the clock signal input to these components is then restarted such that the processor can continue normal execution.
摘要翻译：时钟调节机制关闭某些处理器组件以最小化功耗。处理器检测某些总线周期的发布或某些指令的执行，这些指令通常会导致处理器空闲一段时间。控制电路检测指令和/或总线周期的存在，并在该空闲期间关闭驱动某些处理器组件的时钟。然后，控制电路检测处理器响应并发生事件的发生或即将发生。在检测到该事件时，输入到这些组件的时钟信号然后重新启动，使得处理器可以继续正常执行。

24. 发明授权

US5586307A Method and apparatus supplying synchronous clock signals to circuit components 失效
标题翻译：向电路部件提供同步时钟信号的方法和装置
公开(公告)号：US5586307A
公开(公告)日：1996-12-17
申请号：US86044
申请日：1993-06-30
申请人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
发明人： Keng L. Wong , Kelly J. Fitzpatrick , Jeffrey E. Smith
IPC分类号： G06F1/10 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/15 , G06F1/12
CPC分类号： G06F1/3237 , G06F1/10 , G06F1/3203 , G06F1/3287 , Y02B60/1221 , Y02B60/1282
摘要： A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.
摘要翻译：用于集成电路设备的时钟分配系统和时钟中断系统。忽略与匹配级相关的效应，本发明包括时钟分配和中断系统，用于向集成电路器件的各种部件提供小于100皮秒的偏移的时钟信号。本发明利用几级驱动器均匀地提供分布式时钟信号，每级具有RC匹配输入线。本发明有利地位于位于微处理器拓扑周边的集成电路的电源环内的匹配级和时钟驱动器。这样做是为了更好地预测这些线路周围的拓扑，以匹配这些线路的电容。此外，该金属层提供更大的宽度尺寸线（因为顶层可以更厚），每单位面积的电阻较小，并且还通常避免与其它IC组件和电路的空间竞争。本发明另外提供了利用功率管理单元选择性地降低集成设备内的各种组件并使能作为时钟分配系统的组件被包括的网络的能力。

25. 发明授权

US5585745A Method and apparatus for reducing power consumption in digital electronic circuits 失效
标题翻译：用于降低数字电子电路功耗的方法和装置
公开(公告)号：US5585745A
公开(公告)日：1996-12-17
申请号：US686272
申请日：1996-07-25
申请人： Laura E. Simmons , Rajeev Jayavant
发明人： Laura E. Simmons , Rajeev Jayavant
IPC分类号： G06F1/32 , H03K19/096 , H03K19/00
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282 , Y02B60/32
摘要： An integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks. The clock controller is operative to modulate the input clock in accordance with the signals on the clock control lines to provide modulated clocks to each of the plurality of functional blocks. A method for reducing power consumption includes the steps of: a) receiving control signals from a number of functional blocks; b) selectively deactivating a particular functional block upon a request from that functional block or from another functional block; and c) activating the particular functional block upon a request from another functional block.
摘要翻译：具有功率保存的集成电路包括多个功能块，每个功能块包括数字电路和至少一个输出控制线，以及耦合到控制线的功率控制器。输出控制线根据功能块对数据流方向的了解，开发时钟控制信号。功率控制器通过停用时钟控制信号所指示的不需要的功能块来降低功耗。更具体地说，具有省能的系统包括能够处理数据的多个功能块，每个功能块包括调制时钟输入和反映数据流的方向的N + 1个时钟控制线，其中N是特定功能块的邻居以及具有输入时钟的时钟控制器，所述时钟控制器耦合到调制时钟输入和功能块的时钟控制线。时钟控制器可操作以根据时钟控制线上的信号调制输入时钟，以向多个功能块中的每一个提供调制时钟。一种降低功耗的方法包括以下步骤：a）从多个功能块接收控制信号; b）根据来自该功能块或另一功能块的请求选择性地去激活特定功能块; 以及c）在来自另一功能块的请求时激活所述特定功能块。

26. 发明授权

US5504909A Power management apparatus collocated on the same integrated circuit as the functional unit that it manages 失效
标题翻译：电源管理装置与其管理的功能单元位于同一集成电路上
公开(公告)号：US5504909A
公开(公告)日：1996-04-02
申请号：US185185
申请日：1994-01-21
申请人： Larry D. Webster , Ehud Pardo
发明人： Larry D. Webster , Ehud Pardo
IPC分类号： G06F1/32 , G06F15/00 , G06F11/30
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282
摘要： A power management apparatus that controls the use of power within an integrated circuit. A first embodiment gates integrated circuit power on or off concurrently with switches inserted between the co-resident functional circuit I/O nets and the integrated circuit I/O pads. A second embodiment instantiates the power management apparatus on an integrated circuit by itself for connection to external integrated circuits. Buffering or sequencing is provided for both embodiments.
摘要翻译：控制集成电路内的电力使用的电力管理装置。第一实施例与插入在共驻功能电路I / O网络和集成电路I / O焊盘之间的开关同时开启或关闭集成电路电源。第二实施例将集成电路本身的功率管理装置实例化为与外部集成电路的连接。为两个实施例提供缓冲或排序。

27. 发明授权

US5502689A Clock generator capable of shut-down mode and clock generation method 失效
标题翻译：具有关闭模式和时钟发生方式的时钟发生器
公开(公告)号：US5502689A
公开(公告)日：1996-03-26
申请号：US201077
申请日：1994-02-24
申请人： Joseph W. Peterson , Alan F. Hendrickson , Dale E. Gulick , Dean Grumlose
发明人： Joseph W. Peterson , Alan F. Hendrickson , Dale E. Gulick , Dean Grumlose
IPC分类号： H04B1/16 , G06F1/04 , G06F1/32 , H04B1/38 , H04B7/26 , G04F5/00 , G06F1/00
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282 , Y02B60/32
摘要： A clock generator and interrupt bypass circuit for use in reducing the power consumption of the electrical system in which they are implemented. The clock generator provides module clock signals for sequencing modules within the same electrical system, and is capable of generating those module clock signals when in an active mode, and of not generating those module clock signals when in a stand-by mode. The clock generator is further capable of providing a delay of a predetermined length from a request to enter shut-down mode to actual entry into shut-down mode, allowing time to prepare the electrical system for shut-down mode. The interrupt bypass circuit provides a means of leaving shut-down mode in the event that the relevant interrupt requests have been masked.
摘要翻译：一个时钟发生器和中断旁路电路，用于降低实施电气系统的功耗。时钟发生器为同一电气系统中的排序模块提供模块时钟信号，并且能够在处于活动模式时产生那些模块时钟信号，并且在处于待机模式时不产生这些模块时钟信号。时钟发生器还能够提供从进入关闭模式的请求到实际进入关闭模式的预定长度的延迟，从而允许时间来准备用于关闭模式的电气系统。中断旁路电路提供了在相关中断请求已被屏蔽的情况下关闭模式的方法。

28. 发明授权

US5467042A Low power clocking apparatus and method 失效
标题翻译：低功率计时装置及方法
公开(公告)号：US5467042A
公开(公告)日：1995-11-14
申请号：US149107
申请日：1993-11-08
申请人： Stephen A. Smith , Bryan Richter , Dave M. Singhal
发明人： Stephen A. Smith , Bryan Richter , Dave M. Singhal
IPC分类号： G06F1/32 , H03K3/00
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282
摘要： A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits.
摘要翻译：低功率计时装置和方法被用于通过经配置以选择性地从电子系统或集成电路发送或接收信号的系统总线来耦合到外部系统的电子系统或集成电路来降低功耗。电子系统或集成电路包括多个子电路。每个子电路被配置为在时钟信号的控制下操作，并且还包括用于保持或拒绝时钟信号的装置。一旦电子系统或集成电路中的每个子电路拒绝时钟信号，整数仲裁电路将时钟信号禁止所有子电路。仲裁器电路连续监视系统总线。在检测到子电路需要时钟信号时，仲裁器将重新使能到所有子电路的时钟信号。

29. 发明授权

US5452434A Clock control for power savings in high performance central processing units 失效
标题翻译：高性能中央处理器的节能时钟控制
公开(公告)号：US5452434A
公开(公告)日：1995-09-19
申请号：US913289
申请日：1992-07-14
申请人： James R. MacDonald
发明人： James R. MacDonald
IPC分类号： G06F1/04 , G06F1/32 , G06F9/38
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/3885 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： The invention relates to a clock controller circuit for performing a power saving feature in high performance microprocessors. The invention utilizes two logic gates and a flip flop for disabling a clock signal to an execution unit or ALU when data is not available for the execution unit or ALU. The invention provides a sleep mode or clock idle mode for an execution unit when data is not available for the execution unit because memory units, I/O devices, or internal caches are unable to provide data or instructions to the execution unit. The clock controller circuit disables the clock signals by gating the clock signal to a logic high. The clock controller circuit stops the clock signals in response to a no data available signal from a bus unit and a data required signal from the execution unit.
摘要翻译：本发明涉及一种用于在高性能微处理器中执行省电功能的时钟控制器电路。当数据不可用于执行单元或ALU时，本发明利用两个逻辑门和触发器来禁止对执行单元或ALU的时钟信号。当数据不可用于执行单元时，本发明提供了执行单元的睡眠模式或时钟空闲模式，因为存储单元，I / O设备或内部高速缓存不能向执行单元提供数据或指令。时钟控制器电路通过将时钟信号门控为逻辑高电平来禁止时钟信号。响应于来自总线单元的无数据可用信号和来自执行单元的数据所需信号，时钟控制器电路停止时钟信号。

30. 发明授权

US4171539A Power strobed digital computer system 失效
标题翻译：电源选通数字电脑系统
公开(公告)号：US4171539A
公开(公告)日：1979-10-16
申请号：US861592
申请日：1977-12-19
申请人： David A. Tawfik , Martin W. Feintuch
发明人： David A. Tawfik , Martin W. Feintuch
IPC分类号： G06F15/00 , G06F1/32 , G06F1/00
CPC分类号： G06F1/3228 , G06F1/3203 , G06F1/3287 , Y02B60/1282
摘要： For use with a digital computer system utilizing a processing unit having a higher computational capability than required, means for removing power from system components not required to remember computational variables when the processing unit has completed its prescribed tasks.
摘要翻译：为了与利用具有比所需的更高计算能力的处理单元的数字计算机系统一起使用的装置，用于在处理单元完成其规定任务时从计算变量不需要记住的系统组件的功率消除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式