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21. 发明授权

US09065480B1 Digital-to-analog converter apparatus having a reconfigurable resistor-capacitor circuit 有权
标题翻译：具有可重新配置的电阻 - 电容电路的数模转换器装置
公开(公告)号：US09065480B1
公开(公告)日：2015-06-23
申请号：US14290981
申请日：2014-05-29
申请人： MEDIATEK INC.
发明人： Wei-Hsin Tseng
IPC分类号： H03M1/06 , H03M1/68 , H03M1/00 , H03M1/70
CPC分类号： H03M3/388 , H03M3/50
摘要： A digital-to-analog converter apparatus includes a digital-to-analog converter, a resistor-capacitor circuit, a quantizer and a controller. The resistor-capacitor circuit includes an operational amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor, a first switch and a second switch. The digital-to-analog converter may generate a plurality of currents. The quantizer may generate a plurality of offset values. The controller may control coupling of the plurality of currents to the operational amplifier.
摘要翻译：数模转换器装置包括数模转换器，电阻 - 电容电路，量化器和控制器。电阻电容器电路包括运算放大器，第一电容器，第二电容器，第一电阻器，第二电阻器，第一开关和第二开关。数模转换器可以产生多个电流。量化器可以产生多个偏移值。控制器可以控制多个电流到运算放大器的耦合。

22. 发明申请

US20150061911A1 Conversion of a Discrete Time Quantized Signal into a Continuous Time, Continuously Variable Signal 有权
标题翻译：将离散时间量化信号转换为连续时间，连续可变信号
公开(公告)号：US20150061911A1
公开(公告)日：2015-03-05
申请号：US14537122
申请日：2014-11-10
申请人： SYNTROPY SYSTEMS, LLC
发明人： Christopher Pagnanelli
IPC分类号： H03M1/66
CPC分类号： H03M1/661 , H03F1/3247 , H03M1/747 , H03M3/30 , H03M3/358 , H03M3/50 , H03M3/502 , H03M7/3026 , H03M7/3033 , H04L27/04
摘要： Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.
摘要翻译：尤其提供了用于将离散时间量化信号转换成连续时间连续可变信号的系统，装置，方法和技术。示例性转换器优选地包括：（1）多个过采样转换器，每个处理不同的频带，并行操作; （2）多速率（即多相）Δ-Σ调制器（优选二阶或更高）; （3）多位量化器; （4）多位到可变电平信号转换器，如电阻梯形网络或电流源网络; （5）自适应非线性比特映射以补偿多比特到可变电平信号转换器中的不匹配（例如，通过模拟这样的失配，然后将所得到的噪声移动到频率范围，其中将被滤波掉相应的带通（重建）滤波器）; （6）多频带（例如可编程噪声传递函数响应）带通Δ-Σ调制器; 和/或（7）用于消除由模拟信号带通（重构）滤波器组引入的噪声和失真的数字预失真线性化器（DPL）。

23. 发明授权

US08970414B2 Tri-level digital-to-analog converter 有权
公开(公告)号：US08970414B2
公开(公告)日：2015-03-03
申请号：US13931498
申请日：2013-06-28
申请人： Broadcom Corporation
发明人： David Stoops , Min Gyu Kim , Vinod Jayakumar
IPC分类号： H03M3/00
CPC分类号： H03M3/50 , H03M3/502
摘要： Methods, systems, and apparatuses for converting a digital input signal to an analog output signal are disclosed. A first delta-sigma modulator receives a common mode reference signal and generates a common mode control signal. A data delta-sigma modulator receives a digital input signal and generates a modulated digital input signal. A shuffler receives the modulated digital input signal and the common mode control signal and generates a shuffled digital input signal. A digital to analog converter (DAC) has a plurality of tri-level unit DAC elements each receiving a corresponding portion of the shuffled digital input signal as a first input signal, and receiving second and third input signals. The tri-level unit DAC elements have first outputs coupled together generating a first output signal and second outputs coupled together generating a second output signal. An operational amplifier receives the first and second output signals and generates the analog output signal.

24. 发明授权

US08964860B2 Digital modulator 有权
标题翻译：数字调制器
公开(公告)号：US08964860B2
公开(公告)日：2015-02-24
申请号：US14115566
申请日：2012-03-13
申请人： Shinichi Hori
发明人： Shinichi Hori
IPC分类号： H04B14/06 , H04L27/12 , H03M3/00
CPC分类号： H04L27/12 , H03F3/217 , H03F3/24 , H03M3/48 , H03M3/50
摘要： To provide a digital modulator including: a signal adjuster (105) which is provided with a plurality of output lines, and which outputs, to the output line, which corresponds to a range to which a level of an input signal belongs, a signal of a level corresponding to the level of the input signal; a plurality of internal digital modulators (111-1 to 111-N), each of which is provided so as to correspond to each of the plurality of output lines and carries out delta-sigma modulation on the signal of the corresponding output line to output the modulated signal; and an encoder (113) which encodes the plurality of modulated signals respectively outputted by the plurality of internal digital modulators.
摘要翻译：提供一种数字调制器，包括：信号调节器（105），其设有多条输出线，并且输出到与输入信号的电平所属的范围相对应的输出线的信号对应于输入信号电平的电平; 多个内部数字调制器（111-1至111-N），每个内部数字调制器（111-1至111-N）被提供以对应于多个输出线中的每一个，并且对相应输出线的信号执行Δ-Σ调制以输出调制信号; 以及对由多个内部数字调制器分别输出的多个调制信号进行编码的编码器（113）。

25. 发明授权

US08952837B2 Multi-rate sigma delta digital-to-analog converter 有权
标题翻译：多速率Σ-Δ数模转换器
公开(公告)号：US08952837B2
公开(公告)日：2015-02-10
申请号：US14019246
申请日：2013-09-05
申请人： Broadcom Corporation
发明人： Min Gyu Kim , Dongtian Lu , Todd L. Brooks
IPC分类号： H03M3/02 , H03M3/00
CPC分类号： H03M3/414 , H03M3/32 , H03M3/50 , H03M7/3022
摘要： A multi-rate sigma delta digital-to-analog converter may include a signal input and a signal output, and multiple modulators. A first of the modulator may convert a digital input signal on the signal input to an analog output signal on the signal output. Subsequent of the multiple modulators may shape and cancel quantization noise received from a proceeding modulator. One of the modulators may operate at a higher frequency than does another of the multiple modulation loops.
摘要翻译：多速率Σ-Δ数模转换器可以包括信号输入和信号输出以及多个调制器。调制器中的第一个可以将信号输入上的数字输入信号转换为信号输出上的模拟输出信号。随后的多个调制器可以形成和消除从前进的调制器接收的量化噪声。调制器中的一个可以以比多个调制回路中的另一个更高的频率工作。

26. 发明授权

US08941520B2 Resistor-based Σ-ΔDAC 有权
标题翻译：基于电阻和电阻的DAC
公开(公告)号：US08941520B2
公开(公告)日：2015-01-27
申请号：US13995156
申请日：2011-09-30
申请人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
发明人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： H03M3/00 , H03M1/08 , H03M1/80 , H03M1/78 , H03M1/74 , H03M1/00 , H03M1/12 , G09G3/36
CPC分类号： H03M3/50 , G09G3/3688 , H03M1/00 , H03M1/0863 , H03M1/12 , H03M1/747 , H03M1/785 , H03M1/808 , H03M3/30 , H03M3/502
摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.
摘要翻译：逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。电阻梯形网络的每个电阻器包括输入端和输出端。每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。在输出节点处产生基于多位输入信号的输出电压。在一个示例性实施例中，多比特输入信号是Σ-Δ（＆Sgr＆amp; Dgr）调制的多位输入信号。在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

27. 发明申请

US20140375488A1 TRI-LEVEL DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：三电平数字到模拟转换器
公开(公告)号：US20140375488A1
公开(公告)日：2014-12-25
申请号：US13931498
申请日：2013-06-28
申请人： Broadcom Corporation
发明人： David Stoops , Min Gyu Kim , Vinod Jayakumar
IPC分类号： H03M3/00
CPC分类号： H03M3/50 , H03M3/502
摘要： Methods, systems, and apparatuses for converting a digital input signal to an analog output signal are disclosed. A first delta-sigma modulator receives a common mode reference signal and generates a common mode control signal. A data delta-sigma modulator receives a digital input signal and generates a modulated digital input signal. A shuffler receives the modulated digital input signal and the common mode control signal and generates a shuffled digital input signal. A digital to analog converter (DAC) has a plurality of tri-level unit DAC elements each receiving a corresponding portion of the shuffled digital input signal as a first input signal, and receiving second and third input signals. The tri-level unit DAC elements have first outputs coupled together generating a first output signal and second outputs coupled together generating a second output signal. An operational amplifier receives the first and second output signals and generates the analog output signal.
摘要翻译：公开了用于将数字输入信号转换为模拟输出信号的方法，系统和装置。第一Δ-Σ调制器接收共模参考信号并产生共模控制信号。数据Δ-Σ调制器接收数字输入信号并产生调制数字输入信号。洗牌器接收调制数字输入信号和共模控制信号，并产生混洗数字输入信号。数模转换器（DAC）具有多个三电平单元DAC元件，每个三电平单元DAC元件接收混频数字输入信号的相应部分作为第一输入信号，并且接收第二和第三输入信号。三电平单元DAC元件具有耦合在一起的第一输出产生第一输出信号和耦合在一起的第二输出产生第二输出信号。运算放大器接收第一和第二输出信号并产生模拟输出信号。

28. 发明申请

US20140301571A1 SYSTEMS AND METHODS FOR GENERATING A DIGITAL OUTPUT SIGNAL IN A DIGITAL MICROPHONE SYSTEM 审中-公开
标题翻译：在数字麦克风系统中产生数字输出信号的系统和方法
公开(公告)号：US20140301571A1
公开(公告)日：2014-10-09
申请号：US14247686
申请日：2014-04-08
申请人： Cirrus Logic, Inc.
发明人： John L. Melanson , John C. Tucker
IPC分类号： H04R3/00
CPC分类号： H04R3/02 , H03F1/26 , H03F3/16 , H03F2200/372 , H03M3/00 , H03M3/39 , H03M3/424 , H03M3/458 , H03M3/50 , H03M7/3026 , H03M7/3028 , H04R3/00 , H04R3/002 , H04R3/007 , H04R19/04 , H04R29/001
摘要： In accordance with embodiments of the present disclosure, a digital microphone system may include a microphone transducer and a digital processing system. The microphone transducer may be configured to generate an analog input signal indicative of audio sounds incident upon the microphone transducer. The digital processing system may be configured to convert the analog input signal into a first digital signal having three or more quantization levels, and in the digital domain, process the first digital signal to convert the first digital signal into a second digital signal having two quantization levels.
摘要翻译：根据本公开的实施例，数字麦克风系统可以包括麦克风换能器和数字处理系统。麦克风换能器可以被配置为产生指示入射到麦克风换能器上的音频声音的模拟输入信号。数字处理系统可以被配置为将模拟输入信号转换成具有三个或更多个量化级别的第一数字信号，并且在数字域中处理第一数字信号以将第一数字信号转换成具有两个量化的第二数字信号水平。

29. 发明申请

US20140258569A1 SIGNAL PROCESSING SYSTEM AND ASSOCIATED METHOD 有权
标题翻译：信号处理系统及相关方法
公开(公告)号：US20140258569A1
公开(公告)日：2014-09-11
申请号：US14173870
申请日：2014-02-06
申请人： MEDIATEK INC.
发明人： Chien-Chung Yang , Chia-Feng Chiang , Chien-Ming Chen
IPC分类号： G06F13/10
CPC分类号： H03M3/50 , G06F3/00 , G06F11/1443 , G06F11/3041 , G06F11/3051 , G06F13/10 , G06F13/12 , H03M3/462 , H03M3/508
摘要： The present invention provides a signal processing system and associated method. The signal processing system includes converter(s) for conversion between digital and analog, each converter includes multiple serially coupled units forming multiple frequency interfaces respectively associating with different frequencies, and each converter is partitioned, at a selected frequency interface, to a first portion and a second portion respectively formed in the first chip and the second chip. The partitioning frequency interface is selected to reduce implement cost.
摘要翻译：本发明提供一种信号处理系统及其相关方法。信号处理系统包括用于在数字和模拟之间转换的转换器，每个转换器包括形成分别与不同频率相关联的多个频率接口的多个串行耦合单元，并且每个转换器在选定的频率接口处被划分到第一部分和分别形成在第一芯片和第二芯片中的第二部分。选择分区频率接口以降低实施成本。

30. 发明申请

US20130271304A1 Continuous Time Analogue/Digital Converter 有权
标题翻译：连续时间模拟/数字转换器
公开(公告)号：US20130271304A1
公开(公告)日：2013-10-17
申请号：US13914145
申请日：2013-06-10
申请人： Centre National de Recherche Scientifique (CNRS) , STMicroelectronics SA
发明人： Didier Belot , Jean-Baptiste Begueret , Yann Deval , Dominique Dallet , André Mariano
IPC分类号： H03M3/00
CPC分类号： H03M3/458 , H03M3/402 , H03M3/484 , H03M3/50
摘要： Continuous time analogue/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analogue input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).
摘要翻译：连续时间模拟/数字转换器，包括被配置为接收模拟输入信号（x（t））并且包括其斩波频率等于采样的一半的高通滤波装置（MF）的Σ-Δ调制器（MSD1）调制器（MSD1）的量化装置（QTZ）的频率（Fs）。

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