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1. 发明申请

US20130271305A1 RESISTOR-BASED SIGMA-DELTA DAC 有权
标题翻译：基于电阻的SIGMA-DELTA DAC
公开(公告)号：US20130271305A1
公开(公告)日：2013-10-17
申请号：US13995156
申请日：2011-09-30
申请人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
发明人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： H03M3/00 , H03M1/78
CPC分类号： H03M3/50 , G09G3/3688 , H03M1/00 , H03M1/0863 , H03M1/12 , H03M1/747 , H03M1/785 , H03M1/808 , H03M3/30 , H03M3/502
摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.
摘要翻译：逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。电阻梯形网络的每个电阻器包括输入端和输出端。每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。在输出节点处产生基于多位输入信号的输出电压。在一个示例性实施例中，多位输入信号是Σ-Δ（SigmaDelta）调制的多位输入信号。在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

2. 发明授权

US08941520B2 Resistor-based Σ-ΔDAC 有权
标题翻译：基于电阻和电阻的DAC
公开(公告)号：US08941520B2
公开(公告)日：2015-01-27
申请号：US13995156
申请日：2011-09-30
申请人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
发明人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： H03M3/00 , H03M1/08 , H03M1/80 , H03M1/78 , H03M1/74 , H03M1/00 , H03M1/12 , G09G3/36
CPC分类号： H03M3/50 , G09G3/3688 , H03M1/00 , H03M1/0863 , H03M1/12 , H03M1/747 , H03M1/785 , H03M1/808 , H03M3/30 , H03M3/502
摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.
摘要翻译：逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。电阻梯形网络的每个电阻器包括输入端和输出端。每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。在输出节点处产生基于多位输入信号的输出电压。在一个示例性实施例中，多比特输入信号是Σ-Δ（＆Sgr＆amp; Dgr）调制的多位输入信号。在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

3. 发明授权

US08390349B1 Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter 有权
标题翻译：次皮秒分辨率分段重新循环随机时间 - 数字转换器
公开(公告)号：US08390349B1
公开(公告)日：2013-03-05
申请号：US13533341
申请日：2012-06-26
申请人： Ashoke Ravi , Ofir Degani , Hyung Seok Kim , Hasnain Lakdawala , Yee W. Li , Paolo Madoglio
发明人： Ashoke Ravi , Ofir Degani , Hyung Seok Kim , Hasnain Lakdawala , Yee W. Li , Paolo Madoglio
IPC分类号： H03L7/06
CPC分类号： G04F10/005 , H03L2207/50
摘要： Disclosed is a method and apparatus to extend TDC resolution to better than 1 ps without incurring a matching and power penalty. Higher resolution can be achieved by segmenting the resolution between a mismatch free re-circulating time-to-digital converter (RTDC) and a stochastic time-to-digital converter (STDC). The disclosed RTDC replicates the same delay element to eliminate mismatch with the required dynamic range (200 ps for a 5 GHz example) and moderate resolution (3-5 ps typical corresponding to 6-7 bits for the 5 GHz case). While the STDC can achieve a resolution of 50 fs but with a range of only 3-5 ps which also corresponds to approximately 6-7 additional bits by exploiting process variations and mismatch to achieve a very fine resolution with limited dynamic range.
摘要翻译：公开了一种将TDC分辨率提高到1ps而不引起匹配和功率损失的方法和装置。可以通过在不匹配的循环时间数字转换器（RTDC）和随机时间 - 数字转换器（STDC）之间分辨分辨率来实现更高的分辨率。所公开的RTDC复制相同的延迟元件以消除与所需动态范围（对于5GHz示例为200ps）和中等分辨率（3-5ps典型对应于5GHz情况下的6-7位）的失配。虽然STDC可以实现50 fs的分辨率，但只有3-5 ps的范围，这也通过利用过程变化和失配来对应于大约6-7个附加位，以获得有限动态范围的非常精细的分辨率。

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