专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20160085615A1 Method and Apparatus for Improving Data Integrity Using Compressed Soft Information 有权
标题翻译：使用压缩软信息提高数据完整性的方法和装置
公开(公告)号：US20160085615A1
公开(公告)日：2016-03-24
申请号：US14493865
申请日：2014-09-23
申请人： MEHRAN NEKUII
发明人： MEHRAN NEKUII
IPC分类号： G06F11/10 , H04L1/00 , H03M13/45
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/23 , H03M13/27 , H03M13/2957 , H03M13/3723 , H03M13/45 , H03M13/6577 , H03M13/6588 , H04L1/0047
摘要： A process capable of employing compression and decompression mechanism to receive and decode soft information is disclosed. The process, in one aspect, is able to receive a data stream formatted with soft information from a communication network such as a wireless network. After identifying a set of bits representing a first logic value from a portion of the data stream in accordance with a predefined soft encoding scheme, the set of bits is compressed into a compressed set of bits. The compressed set of bits which represents the first logic value is subsequently stored in a local memory.
摘要翻译：公开了一种能够采用压缩和解压缩机制来接收和解码软信息的过程。该方法在一个方面能够从诸如无线网络的通信网络接收用软信息格式化的数据流。在根据预定义的软编码方案从数据流的一部分识别表示第一逻辑值的一组位后，将该组比特压缩成一组压缩的比特。表示第一逻辑值的压缩的位组被随后存储在本地存储器中。

22. 发明申请

US20160034353A1 Storage Module and Method for Improved Error Correction by Detection of Grown Bad Bit Lines 有权
标题翻译：存储模块和通过检测生成坏位线改进纠错的方法
公开(公告)号：US20160034353A1
公开(公告)日：2016-02-04
申请号：US14502738
申请日：2014-09-30
申请人： SanDisk Technologies Inc.
发明人： Daniel E. Tuers , Abjiheet Manohar
IPC分类号： G06F11/10 , H03M13/09 , H03M13/11
CPC分类号： G06F11/1076 , G06F11/1012 , G11C29/025 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C2029/0403 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208 , G11C2029/4402 , H03M13/1102 , H03M13/1111 , H03M13/152 , H03M13/3723 , H03M13/451 , H03M13/6325
摘要： A storage module and method are provided for improved error correction by detection of grown bad bit lines. In one embodiment, a storage module is provided comprising a controller and a memory having a plurality of bit lines. The controller detects an uncorrectable error in a code word read from the memory, determines location(s) of grown bad bit line(s) that contributed to the error in the code word being uncorrectable, and uses the determined location(s) of the grown bad bit line(s) to attempt to correct the error in the code word.
摘要翻译：提供了一种存储模块和方法，用于通过检测生长的坏位线来改进纠错。在一个实施例中，提供了包括控制器和具有多个位线的存储器的存储模块。控制器检测从存储器读取的代码字中的不可校正错误，确定有助于代码字中的错误是不可校正的生长坏位线的位置，并使用确定的位置生成坏的位线来尝试纠正代码字中的错误。

23. 发明授权

US09236888B2 Storage device, memory controller and memory control method 有权
标题翻译：存储设备，内存控制器和内存控制方式
公开(公告)号：US09236888B2
公开(公告)日：2016-01-12
申请号：US14306462
申请日：2014-06-17
申请人： Kabushiki Kaisha Toshiba
发明人： Susumu Yamazaki , Kenji Yoshida
IPC分类号： H03M13/00 , H03M13/29 , G06F11/10 , G11C16/26 , G11C11/56
CPC分类号： H03M13/29 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/021 , G11C29/028 , G11C2029/0411 , H03M13/1105 , H03M13/3723 , H03M13/612 , H03M13/6325
摘要： According to an embodiment, a storage device includes: a semiconductor memory that includes a multilevel memory cell, stores a first code word and a second code word, and in which a plurality of memory cells connected to one word line can store a plurality of pages; and a controller. The controller performs error correction processing of the first code word read out from one page among the plurality of pages of the semiconductor memory, and the second code word written in a page other than the page corresponding to the first code word among the plurality of pages, re-reads the first code word when the first code word is uncorrectable and the second code word was able to be corrected by the error correction processing, and determines a bit value of the first code word using a re-read result and the second code word after error correction.
摘要翻译：根据实施例，存储装置包括：半导体存储器，包括多级存储器单元，存储第一代码字和第二代码字，并且其中连接到一条字线的多个存储器单元可以存储多个页面 ; 和控制器。控制器对从半导体存储器的多个页面中的一页读出的第一代码字执行纠错处理，并且将第二代码字写入除了与多个页面中的第一代码字相对应的页面之外的页面中当第一码字不可校正并且第二码字能够通过纠错处理被纠正时重新读取第一码字，并且使用重新读取结果确定第一码字的位值，并且第二码字纠错后的代码字。

24. 发明授权

US09189323B2 Semiconductor storage device and method of controlling the same 有权
标题翻译：半导体存储装置及其控制方法
公开(公告)号：US09189323B2
公开(公告)日：2015-11-17
申请号：US13820159
申请日：2011-12-15
申请人： Toshikatsu Hida , Takashi Oshima , Kouji Watanabe
发明人： Toshikatsu Hida , Takashi Oshima , Kouji Watanabe
IPC分类号： G11C29/00 , G06F11/10 , G06F11/08 , H03M13/15 , H03M13/29 , H03M13/37 , H04L29/08 , G11C29/04 , H03M13/09
CPC分类号： G06F11/10 , G06F11/08 , G06F11/1004 , G06F11/1044 , G06F11/108 , G11C2029/0411 , H03M13/09 , H03M13/1515 , H03M13/152 , H03M13/2906 , H03M13/2927 , H03M13/3723 , H04L67/1097
摘要： According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory, a temporary storage buffer that temporarily stores writing data to be written to the nonvolatile semiconductor memory, and a coding processing unit that divides coding target data of an error correction code into two or more divided data and writes an error correction code obtained by performing an error correction coding process based on the divided data stored in the temporary storage buffer to the temporary storage buffer as an intermediate code.
摘要翻译：根据一个实施例，半导体存储装置包括非易失性半导体存储器，临时存储要写入非易失性半导体存储器的写入数据的临时存储缓冲器，以及将纠错码的编码目标数据分成两部分的编码处理单元或更多的分割数据，并将通过基于存储在临时存储缓冲器中的划分数据执行纠错编码处理而获得的纠错码写入临时存储缓冲器作为中间代码。

25. 发明授权

US09184767B2 Scoring variable nodes for low density parity check code decoding 有权
标题翻译：为低密度奇偶校验码解码得分变量节点
公开(公告)号：US09184767B2
公开(公告)日：2015-11-10
申请号：US14069138
申请日：2013-10-31
申请人： Fusion-io, Inc.
发明人： Mark Vernon
IPC分类号： H03M13/11 , H03M13/25
CPC分类号： H03M13/1108 , H03M13/1111 , H03M13/1117 , H03M13/255 , H03M13/3723 , H03M13/658
摘要： Apparatuses, systems, methods, and computer program products are disclosed for error correcting code (ECC) decoding. A score module is configured to assign a score to a variable node of low density parity check (LDPC) code decoder. The LDPC code decoder may include a plurality of variable nodes associated with a plurality of check nodes. The plurality of variable nodes may correspond to bits of a received code word. The score for the variable node may be based on a count of unsatisfied check nodes associated with the variable node. A variable node update module is configured to update the variable node based on the score. A check node update module is configured to update one or more of the check nodes based on the updated variable node.
摘要翻译：公开了用于纠错码（ECC）解码的装置，系统，方法和计算机程序产品。分数模块被配置为将分数分配给低密度奇偶校验（LDPC）码解码器的可变节点。 LDPC码解码器可以包括与多个校验节点相关联的多个变量节点。多个可变节点可以对应于接收的码字的比特。可变节点的分数可以基于与变量节点相关联的不满足的校验节点的计数。变量节点更新模块被配置为基于分数来更新变量节点。校验节点更新模块被配置为基于更新的变量节点更新一个或多个校验节点。

26. 发明申请

US20150288387A1 METHODS AND APPARATUS FOR DECODING 审中-公开
标题翻译：用于解码的方法和装置
公开(公告)号：US20150288387A1
公开(公告)日：2015-10-08
申请号：US14437575
申请日：2012-12-14
申请人： NOKIA CORPORATION
发明人： Xianjun Jiao , Berg Heikki , Canfeng Chen
IPC分类号： H03M13/37 , G06F11/10
CPC分类号： H03M13/3746 , G06F11/1076 , H03M13/2957 , H03M13/3723 , H03M13/3972 , H03M13/6525 , H03M13/6561 , H03M13/6569
摘要： Systems and techniques for decoding of data are described. A plurality of sub-decoders are defined, with the number of sub-decoders being limited only by a number of bits of a codeblock to be processed. A number of iterations is defined for the sub-decoders based on a desired maximum block error rate. Sub-decoders may run asynchronously.
摘要翻译：描述用于数据解码的系统和技术。定义了多个子解码器，其中子解码器的数量仅由要处理的码块的位数限制。基于期望的最大块错误率为子解码器定义多个迭代。子解码器可能异步运行。

27. 发明授权

US09083381B2 Method of determining at least one parameter of an error-correcting code implemented on transmission, corresponding device and computer program 有权
标题翻译：确定在传输，对应的设备和计算机程序上实现的纠错码的至少一个参数的方法
公开(公告)号：US09083381B2
公开(公告)日：2015-07-14
申请号：US13808837
申请日：2011-07-06
申请人： Roland Gautier , Eric Rannou , Mélanie Marazin , Gilles Burel
发明人： Roland Gautier , Eric Rannou , Mélanie Marazin , Gilles Burel
IPC分类号： H03M13/00 , H03M13/33 , H03M13/37 , H03M13/05 , H03M13/11 , H03M13/23 , H03M13/29
CPC分类号： H03M13/00 , H03M13/05 , H03M13/11 , H03M13/23 , H03M13/29 , H03M13/2957 , H03M13/33 , H03M13/3723 , H03M13/6508 , H03M13/6513 , H03M13/6516
摘要： A method and apparatus are provided for determining at least one parameter of an error correcting code implemented on transmission, termed a “coding parameter”, by analyzing a binary train received. The method implements a first step making it possible to coarsely define said at least one coding parameter, and a second step making it possible to refine said at least one coding parameter.
摘要翻译：提供一种方法和装置，用于通过分析所接收的二进制串来确定被称为“编码参数”的传输中实现的纠错码的至少一个参数。该方法实现了可以粗略地定义所述至少一个编码参数的第一步骤，以及使得可以细化所述至少一个编码参数的第二步骤。

28. 发明授权

US08910029B2 Iterative decoder 有权
标题翻译：迭代解码器
公开(公告)号：US08910029B2
公开(公告)日：2014-12-09
申请号：US13022775
申请日：2011-02-08
申请人： Maria Fresia , Jens Berkmann , Axel Huebner
发明人： Maria Fresia , Jens Berkmann , Axel Huebner
IPC分类号： H03M13/39 , H03M13/37 , H03M13/29
CPC分类号： H03M13/3972 , H03M13/296 , H03M13/3723
摘要： An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration. A first forward/backward decoding scheme is used in a first iteration and a second forward/backward decoding scheme is used in a second iteration. The first and second decoding schemes are different in view of forward and backward processing.
摘要翻译：用于解码码块的迭代解码器包括被配置为在每个解码迭代中在码块或码子块上执行前向和后向递归的计算单元。在第一迭代中使用第一前向/后向解码方案，并且在第二次迭代中使用第二前向/后向解码方案。鉴于前向和后向处理，第一和第二解码方案是不同的。

29. 发明申请

US20140310568A1 RECEIVER, COMMUNICATION DEVICE, AND COMMUNICATION METHOD 审中-公开
标题翻译：接收机，通信设备和通信方法
公开(公告)号：US20140310568A1
公开(公告)日：2014-10-16
申请号：US14359402
申请日：2013-01-15
申请人： Wataru Matsumoto , Yoshikuni Miyata , Kenya Sugihara
发明人： Wataru Matsumoto , Yoshikuni Miyata , Kenya Sugihara
IPC分类号： H03M13/11
CPC分类号： H03M13/1105 , H03M13/1102 , H03M13/1111 , H03M13/1191 , H03M13/336 , H03M13/3723 , H03M13/6325 , H04L1/0047 , H04L1/0057
摘要： A Sum-product decoder 17 carries out soft-decision iterative decoding on a received signal s′(t) received by a signal receiving unit 12 by using an extended check matrix Hd which is a combination of a matrix D in which differential modulation by a differential modulator 3 is replaced by a check matrix and a check matrix H for error correcting codes to carry out error correction decoding on an information sequence bi.
摘要翻译：求和积解码器17对由信号接收单元12接收的接收信号s'（t）执行软判决迭代解码，该扩展校验矩阵Hd是矩阵D的组合，其中差分调制由差分调制器3由用于纠错码的校验矩阵和校验矩阵H代替，以对信息序列bi执行纠错解码。

30. 发明授权

US08861652B2 Detecting format of a transport channel 有权
标题翻译：检测传输通道的格式
公开(公告)号：US08861652B2
公开(公告)日：2014-10-14
申请号：US13436845
申请日：2012-03-31
申请人： Chuan-Hsuan Kuo
发明人： Chuan-Hsuan Kuo
IPC分类号： H04L27/06
CPC分类号： H04W56/002 , H03M13/3723 , H03M13/3905 , H03M13/3972 , H04L1/005 , H04W36/18
摘要： A system and method for determining a transport format of a transport channel is described. A guiding stream is received on a guiding transport channel and a guided stream is received on a guided transport channel. The guided stream is convolutionally decoded to produce a plurality of Viterbi path metrics. A transport format for the guided transport channel is selected from possible transport formats. The possible transport formats are determined by information provided on the guiding transport channel. The selection of the transport format is based at least in part on a metric computed from a combination of the Viterbi path metrics.
摘要翻译：一种用于确定传输信道的传输格式的系统和方法进行说明。在引导传输信道上接收引导流，并且在被引导的传输信道上接收引导流。被引导流被卷积解码以产生多个维特比路径度量。用于引导传输信道的传输格式从可能的传输格式选择。可能的传输格式由在引导传输信道上提供的信息确定。传输格式的选择至少部分地基于从维特比路径度量的组合计算的度量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式