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1. 发明申请

US20160266974A1 MEMORY CONTROLLER, DATA STORAGE DEVICE AND DATA WRITE METHOD 审中-公开
标题翻译：存储控制器，数据存储设备和数据写入方法
公开(公告)号：US20160266974A1
公开(公告)日：2016-09-15
申请号：US14753780
申请日：2015-06-29
申请人： Kabushiki Kaisha Toshiba
发明人： Jun ICHISHIMA , Kenji Yoshida , Yoriharu Takai , Susumu Yamazaki , Norifumi Tsuboi
IPC分类号： G06F11/10 , G06F3/06 , G11C29/52
CPC分类号： G06F11/1072 , G06F11/1048 , G11C29/52 , G11C2029/0411
摘要： According to one embodiment, a memory controller includes a bank controller including a queuing part queuing commands associated with a bank and having a first flag associated with each of the commands, the bank controller executing the commands in order, a data controller transferring write data to the bank when a particular command to be executed among the commands is a write command associated with one of physical addresses in the bank, and a parity controller generating parity data for restoring the write data based on a value of a first flag associated with the particular command, before execution of the particular command is completed.
摘要翻译：根据一个实施例，存储器控制器包括一个存储体控制器，其包括排队部分，排队与一个存储体相关联的命令，并且具有与每个命令相关联的第一标志，存储体控制器按顺序执行命令，数据控制器将写数据传送到当所述命令中要执行的特定命令是与所述存储体中的一个物理地址相关联的写入命令时，所述存储体，以及奇偶校验控制器，用于基于与所述特定数据相关联的第一标志的值生成用于恢复所述写入数据的奇偶校验数据命令，在执行特定命令完成之前。

2. 发明申请

US20140201427A1 STORAGE CONTROL APPARATUS, DATA STORAGE APPARATUS AND METHOD FOR STORAGE CONTROL 审中-公开
标题翻译：存储控制装置，数据存储装置和存储控制方法
公开(公告)号：US20140201427A1
公开(公告)日：2014-07-17
申请号：US13941239
申请日：2013-07-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kazuya Takada , Kenji Yoshida , Hideo Shimokawa , Susumu Yamazaki
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/068
摘要： According to one embodiment, a storage control apparatus includes a first buffer controller and a second buffer controller. The first buffer controller is configured to store data of a first unit in each of data buffer regions, and the data of the first unit is transmitted from a host and written in a nonvolatile memory, or read from the nonvolatile memory and transmitted to the host. The second buffer controller is configured to independently transmit data of a second unit from the data buffer region corresponding to a bank prepared for transmission when data is written in the nonvolatile memory, and to independently transmit data of the second unit from a bank to be read to the data buffer region corresponding to the bank to be read when data is transmitted to the host.
摘要翻译：根据一个实施例，存储控制装置包括第一缓冲器控制器和第二缓冲器控制器。第一缓冲器控制器被配置为存储每个数据缓冲区中的第一单元的数据，并且第一单元的数据从主机发送并写入非易失性存储器中，或者从非易失性存储器读取并发送到主机。第二缓冲器控制器被配置为当数据被写入到非易失性存储器中时，从与准备传输的存储体对应的数据缓冲器区域独立地发送第二单元的数据，并且从要读取的存储体中独立地发送第二单元的数据当数据被发送到主机时，对应于要读取的存储体的数据缓冲器区域。

3. 发明授权

US09236888B2 Storage device, memory controller and memory control method 有权
标题翻译：存储设备，内存控制器和内存控制方式
公开(公告)号：US09236888B2
公开(公告)日：2016-01-12
申请号：US14306462
申请日：2014-06-17
申请人： Kabushiki Kaisha Toshiba
发明人： Susumu Yamazaki , Kenji Yoshida
IPC分类号： H03M13/00 , H03M13/29 , G06F11/10 , G11C16/26 , G11C11/56
CPC分类号： H03M13/29 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/021 , G11C29/028 , G11C2029/0411 , H03M13/1105 , H03M13/3723 , H03M13/612 , H03M13/6325
摘要： According to an embodiment, a storage device includes: a semiconductor memory that includes a multilevel memory cell, stores a first code word and a second code word, and in which a plurality of memory cells connected to one word line can store a plurality of pages; and a controller. The controller performs error correction processing of the first code word read out from one page among the plurality of pages of the semiconductor memory, and the second code word written in a page other than the page corresponding to the first code word among the plurality of pages, re-reads the first code word when the first code word is uncorrectable and the second code word was able to be corrected by the error correction processing, and determines a bit value of the first code word using a re-read result and the second code word after error correction.
摘要翻译：根据实施例，存储装置包括：半导体存储器，包括多级存储器单元，存储第一代码字和第二代码字，并且其中连接到一条字线的多个存储器单元可以存储多个页面 ; 和控制器。控制器对从半导体存储器的多个页面中的一页读出的第一代码字执行纠错处理，并且将第二代码字写入除了与多个页面中的第一代码字相对应的页面之外的页面中当第一码字不可校正并且第二码字能够通过纠错处理被纠正时重新读取第一码字，并且使用重新读取结果确定第一码字的位值，并且第二码字纠错后的代码字。

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