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21. 发明授权

US09496039B2 Storage device and method for performing interruption control thereof 有权
标题翻译：用于执行其中断控制的存储装置和方法
公开(公告)号：US09496039B2
公开(公告)日：2016-11-15
申请号：US14408535
申请日：2013-06-15
申请人： MEMBLAZE TECHNOLOGY (BEIJING) CO., LTD.
发明人： Xuebing Yin , Yilei Wang
IPC分类号： G11C16/10 , G06F3/06 , G06F13/28
CPC分类号： G11C16/10 , G06F3/0611 , G06F3/0656 , G06F3/0679 , G06F12/0246 , G06F12/0871 , G06F13/28 , G06F2212/1016 , G06F2212/1056 , G06F2212/313 , G06F2212/7203 , G11C2207/2245
摘要： A storage device includes a flash memory and a buffer memory. A method of controlling interrupts includes: receiving data to be written to the storage device from an information processing device; writing the received data to be written to the storage device to the buffer memory; fetching the data in the buffer memory and writing the data to the flash memory; in which, after writing the received data to be written to the storage device to the buffer memory, if the amount of data in the buffer memory is less than the predetermined threshold, then sending a message indicating the completion of the write operation to the information processing device.
摘要翻译：存储装置包括闪速存储器和缓冲存储器。控制中断的方法包括：从信息处理装置接收要写入存储装置的数据; 将要写入存储装置的接收数据写入缓冲存储器; 将数据读取到缓冲存储器中并将数据写入闪速存储器; 其中，在将要写入存储装置的接收数据写入缓冲存储器之后，如果缓冲存储器中的数据量小于预定阈值，则向信息发送指示写入操作完成的消息处理装置。

22. 发明授权

US09443579B2 VSL-based VT-compensation and analog program scheme for NAND array without CSL 有权
标题翻译：基于VSL的VT补偿和无CSL的NAND阵列的模拟程序方案
公开(公告)号：US09443579B2
公开(公告)日：2016-09-13
申请号：US14828427
申请日：2015-08-17
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C5/02 , G11C11/56 , G11C16/10 , G11C16/26 , G11C16/04 , G11C16/34 , G11C7/18 , G11C16/08
CPC分类号： G11C11/5635 , G11C7/18 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C16/3459 , G11C2207/2245 , G11C2211/5641
摘要： A YUKAI NAND array comprising multiple strings of all TLC and mixed TLC+SLC memory cells associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) with full BL-shielding without wasting extra silicon area and without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding to perform concurrent ABL, AnP and Alt-WL program under multi-passes program schemes with LBL program voltage compensations and half-BL Odd/Even program-verify and read operations with individual VSL-based Vt-compensation to mitigate high WL-WL and BL-BL coupling effects.
摘要翻译： YUKAI NAND阵列包括与分层全局/局部位线（GBL / LBL）相关联的所有TLC和混合TLC + SLC存储器单元的多个串，每个串与一个LBL相关联并且具有相邻的LBL作为专用本地源极线（LSL ）具有完全的BL屏蔽，而不浪费额外的硅面积，没有通用的源极线连接所有的串。每个LBL与通过插入每个串中的一对虚拟单元选择的奇数或偶数字符串进行交织关联，并且用作具有完全BL屏蔽的一个片上PCACHE寄存器，以执行并行ABL，AnP和Alt-WL 在具有LBL程序电压补偿和半BL奇偶校验和读取操作的多通程序方案下使用单独的基于VSL的Vt补偿来减轻WL-WL和BL-BL耦合效应。

23. 发明申请

US20160231930A1 METHODS FOR OPERATING A DISTRIBUTED CONTROLLER SYSTEM IN A MEMORY DEVICE 有权
标题翻译：在存储器件中操作分布式控制器系统的方法
公开(公告)号：US20160231930A1
公开(公告)日：2016-08-11
申请号：US15098574
申请日：2016-04-14
申请人： MICRON TECHNOLOGY, INC.
发明人： Luca De Santis , Luigi Pilolli
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0875 , G06F12/0893 , G06F13/1668 , G06F2212/2022 , G06F2212/452 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/16 , G11C11/4074 , G11C11/4096 , G11C16/06 , G11C16/10 , G11C2207/2245 , Y02D10/13 , Y02D10/14
摘要： Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.
摘要翻译：用于操作存储器设备中的分布式控制器系统的方法包括接收读取命令，主控制器响应于读取命令向数据高速缓存控制器生成指示，并且数据高速缓存控制器从存储器设备的存储器阵列接收数据响应指示。

24. 发明授权

US09304913B2 Mixed memory type hybrid cache 有权
标题翻译：混合内存类型混合缓存
公开(公告)号：US09304913B2
公开(公告)日：2016-04-05
申请号：US13843190
申请日：2013-03-15
申请人： QUALCOMM Incorporated
发明人： Xiangyu Dong , Jungwon Suh
IPC分类号： G06F12/00 , G06F12/08 , G11C11/16 , G11C11/00 , G11C13/00
CPC分类号： G06F12/0802 , G06F12/08 , G06F12/0846 , G06F12/0851 , G06F12/0893 , G06F2212/1028 , G06F2212/2024 , G06F2212/205 , G06F2212/225 , G11C11/005 , G11C11/1659 , G11C13/0002 , G11C13/004 , G11C13/0069 , G11C14/0081 , G11C2207/2245 , Y02D10/13
摘要： A hybrid cache includes a static random access memory (SRAM) portion and a resistive random access memory portion. Cache lines of the hybrid cache are configured to include both SRAM macros and resistive random access memory macros. The hybrid cache is configured so that the SRAM macros are accessed before the resistive random memory macros in each cache access cycle. While SRAM macros are accessed, the slower resistive random access memory reach a data access ready state.
摘要翻译：混合高速缓存包括静态随机存取存储器（SRAM）部分和电阻随机存取存储器部分。混合高速缓存的高速缓存行被配置为包括SRAM宏和电阻随机存取存储器宏。配置混合高速缓存，以便在每个高速缓存访问周期中的电阻随机存储器宏之前访问SRAM宏。当访问SRAM宏时，较慢的电阻随机存取存储器达到数据访问就绪状态。

25. 发明授权

US09026747B2 Memory device with a logical-to-physical bank mapping cache 有权
标题翻译：具有逻辑到物理库映射缓存的内存设备
公开(公告)号：US09026747B2
公开(公告)日：2015-05-05
申请号：US13718773
申请日：2012-12-18
申请人： Broadcom Corporation
发明人： Weihuang Wang , Chien-Hsien Wu , Mohammad Issa
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08 , G06F12/02 , G06F12/06 , G11C8/00 , G11C7/10
CPC分类号： G06F12/0802 , G06F12/0292 , G06F12/06 , G06F12/0853 , G06F2205/123 , G11C7/1075 , G11C8/00 , G11C2207/2245
摘要： A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.
摘要翻译：本文描述了具有支持多个读取和写入访问的逻辑到物理（LTP）库映射缓存的存储器件。存储器件允许在相同的时钟周期期间接收至少一个读取操作和一个写入操作。在进入写入操作未被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在对应于与输入写入操作相关联的逻辑存储器组的物理存储体中。在进入写入操作被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在未与任何逻辑存储体相关联的未映射的物理存储体中。

26. 发明授权

US09003121B2 Multi-ported memory with multiple access support 有权
标题翻译：多端口存储器，具有多路访问支持
公开(公告)号：US09003121B2
公开(公告)日：2015-04-07
申请号：US13655723
申请日：2012-10-19
申请人： Broadcom Corporation
发明人： Weihuang Wang , Chien-Hsien Wu
IPC分类号： G06F12/00 , G06F12/08 , G11C7/10
CPC分类号： G06F12/0853 , G11C7/1075 , G11C2207/2245 , Y02D10/13
摘要： A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.
摘要翻译：本文描述了支持多个读取和写入访问的多端口存储器。多端口存储器可以包括大于多端口存储器的每个存储器组的读/写端口的数量的读/写端口。多端口存储器允许在相同时钟周期期间接收至少一个读取操作和至少一个写入操作。在进入写入操作被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在多端口存储器中包括的高速缓存中。该缓存对于写操作和读操作均可访问。在进入写入操作不被至少一个读取操作阻止的情况下，用于该输入写入操作的数据被存储在由该输入写入操作所针对的存储体中。

27. 发明申请

US20140286108A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140286108A1
公开(公告)日：2014-09-25
申请号：US14014944
申请日：2013-08-30
申请人： Kabushiki Kaisha Toshiba
发明人： Masatsugu OGAWA , Teruo Takagiwa
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C7/1012 , G11C7/106 , G11C2207/2245
摘要： According to one embodiment, a semiconductor memory device includes n (n being a natural number of 2 or more) data retention circuits connected to a data input/output terminal; n buses connected respectively to the n data retention circuits; m×n data latch circuits connected to the buses, with m (m being a natural number of 2 or more) data latch circuits being connected per one of the buses; and a selection circuit configured to simultaneously perform data transfer from/to the data retention circuits for a plurality of the data latch circuits in units of a group including the plurality of the data latch circuits, the data latch circuits being divided into the groups so that not all the data latch circuits connected to the same bus are included in the same group.
摘要翻译：根据一个实施例，半导体存储器件包括连接到数据输入/输出端子的n（n是2个或更多个的自然数）数据保持电路; n总线分别连接到n个数据保持电路; 连接到总线的m×n个数据锁存电路，其中m（m是2个或更多的自然数）数据锁存电路每一个总线连接; 以及选择电路，被配置为以包括多个数据锁存电路的组为单位同时对多个数据锁存电路的数据保持电路执行数据传送，数据锁存电路被分成组，使得并不是所有连接到同一总线的数据锁存电路都包含在同一组中。

28. 发明申请

US20140173182A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20140173182A1
公开(公告)日：2014-06-19
申请号：US13831520
申请日：2013-03-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiromitsu KOMAI
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/0646 , G06F13/38 , G11C7/1048 , G11C16/00 , G11C16/24 , G11C2207/005 , G11C2207/2245
摘要： According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.
摘要翻译：根据一个实施例，存储器包括暂时存储对阵列的读/写操作的数据的临时存储区域。临时存储区域包括连接在第一数据总线和第二数据总线之间的钳位FET，连接在第一数据总线与第一电位之间的第一预充电FET，连接在第二数据总线与第一电位之间的第二预充电FET，连接到第一数据总线的第一存储区域和连接到第二数据总线的第二存储区域。控制电路被配置为当数据从第二存储区域传送到第一数据总线时被预充电到第一电位并且第二数据总线被预充电到低于第一电位的第二电位的预充电状态第一个存储区域。

29. 发明申请

US20140052912A1 MEMORY DEVICE WITH A LOGICAL-TO-PHYSICAL BANK MAPPING CACHE 有权
标题翻译：具有逻辑到物理银行映射缓存的存储器件
公开(公告)号：US20140052912A1
公开(公告)日：2014-02-20
申请号：US13718773
申请日：2012-12-18
申请人： BROADCOM CORPORATION
发明人： Weihuang Wang , Chien-Hsien Wu , Mohammad Issa
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0292 , G06F12/06 , G06F12/0853 , G06F2205/123 , G11C7/1075 , G11C8/00 , G11C2207/2245
摘要： A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.
摘要翻译：本文描述了具有支持多个读取和写入访问的逻辑到物理（LTP）库映射缓存的存储器件。存储器件允许在相同的时钟周期期间接收至少一个读取操作和一个写入操作。在进入写入操作未被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在对应于与输入写入操作相关联的逻辑存储器组的物理存储体中。在进入写入操作被至少一个读取操作阻止的情况下，用于该输入写入操作的数据可以存储在未与任何逻辑存储体相关联的未映射的物理存储体中。

30. 发明授权

US08526257B2 Processor with memory delayed bit line precharging 有权
标题翻译：处理器带有内存延迟位线预充电
公开(公告)号：US08526257B2
公开(公告)日：2013-09-03
申请号：US13657502
申请日：2012-10-22
申请人： Marvell World Trade Ltd.
发明人： Sehat Sutardja , Jason T. Su , Hong-Yi Chen , Jason Sheu , Jensen Tjeng
IPC分类号： G11C7/00
CPC分类号： G06F12/0882 , G06F9/30054 , G06F9/30058 , G06F9/3804 , G06F9/3844 , G11C7/06 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C2207/2245 , G11C2207/2281 , Y02D10/13
摘要： A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.
摘要翻译：处理器包括存储器单元阵列，控制模块，预充电电路和放大器模块。控制模块以第一速率生成时钟信号，将预定时间段的第一速率降低到第二速率，并且在预定周期结束时将第二速率调整回第一速率。预充电电路：基于第一速率，对连接到存储器单元阵列的第一行中的存储单元的第一位线进行预充电; 基于第二速率，禁止对第一位线进行预充电; 并且在预定周期结束之后对第一位线进行预充电。放大器模块：基于第一速率，访问存储在第一行的第一指令; 并且基于第二速率，访问存储在阵列的第一行或第二行中的第二指令。

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