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1. 发明申请

US20170084313A1 AMPLIFIER 有权
公开(公告)号：US20170084313A1
公开(公告)日：2017-03-23
申请号：US15181528
申请日：2016-06-14
申请人： Kabushiki Kaisha Toshiba
发明人： Yohei YASUDA , Hiromitsu KOMAI , Kensuke YAMAMOTO , Masaru KOYANAGI , Yasuhiro HIRASHIMA
IPC分类号： G11C7/06 , G11C7/22 , H03F3/16
CPC分类号： G11C7/06 , G11C7/08 , G11C7/22 , H03F3/16
摘要： According to one embodiment, an amplifier includes a first inverter which inverts and delays a first signal to generate a second signal. A second inverter inverts and delays a third signal to generate a fourth signal. A first transistor includes a gate electrode supplied with the second signal. A second transistor includes a gate electrode supplied with the fourth signal. An output terminal is coupled to one terminal of the second transistor and outputs a fifth signal. A third inverter inverts and delays the fifth signal to generate a sixth signal. A first discharge circuit discharges one terminal of the first transistor and the one terminal of the second transistor based on the first, sixth, or fourth signal, and includes one terminal coupled to the other terminal of each of the first and second transistors.

2. 发明申请

US20150254010A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20150254010A1
公开(公告)日：2015-09-10
申请号：US14482697
申请日：2014-09-10
申请人： Kabushiki Kaisha Toshiba
发明人： Hiromitsu KOMAI
IPC分类号： G06F3/06
CPC分类号： G11C29/82 , G06F12/0607 , G11C16/0483 , G11C29/846
摘要： A semiconductor storage device has a cell array, a redundant array provided logically separated from the cell array, a cache memory having a storing area of data read from or written in the cell array by one access, defective column storage to store a column address of a defective column in the cell array, a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage, and a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area at the generation timing of the clock accessing the divided page buffer area.
摘要翻译：半导体存储装置具有单元阵列，与单元阵列逻辑地分离的冗余阵列，具有通过一次存取从单元阵列读取或写入的数据的存储区域的高速缓存存储器，存储列阵列的列地址单元阵列中的有缺陷的列，缺陷列确定模块，用于确定要访问的列地址是否与存储在缺陷列存储器中的列地址匹配;以及时钟发生器，用于生成用于访问每个分割区域的时钟并且当缺陷列确定模块确定存在匹配时，而不是在访问分割页缓冲区的时钟的生成定时处访问划分页缓冲区的时钟。

3. 发明申请

US20170154658A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20170154658A1
公开(公告)日：2017-06-01
申请号：US15432287
申请日：2017-02-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiromitsu KOMAI
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C7/1051 , G11C7/106 , G11C16/0483 , G11C16/08 , G11C2211/5642 , G11C2211/5647
摘要： According to one embodiment, a semiconductor memory device includes a plurality of data latches; and an inverter shared by the plurality of data latches. The inverter is inserted between complementary buses that sandwich the plurality of data latches.

4. 发明申请

US20140173182A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20140173182A1
公开(公告)日：2014-06-19
申请号：US13831520
申请日：2013-03-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiromitsu KOMAI
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/0646 , G06F13/38 , G11C7/1048 , G11C16/00 , G11C16/24 , G11C2207/005 , G11C2207/2245
摘要： According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.
摘要翻译：根据一个实施例，存储器包括暂时存储对阵列的读/写操作的数据的临时存储区域。临时存储区域包括连接在第一数据总线和第二数据总线之间的钳位FET，连接在第一数据总线与第一电位之间的第一预充电FET，连接在第二数据总线与第一电位之间的第二预充电FET，连接到第一数据总线的第一存储区域和连接到第二数据总线的第二存储区域。控制电路被配置为当数据从第二存储区域传送到第一数据总线时被预充电到第一电位并且第二数据总线被预充电到低于第一电位的第二电位的预充电状态第一个存储区域。

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