专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20160141029A1 HEALTH DATA ASSOCIATED WITH A RESISTANCE-BASED MEMORY 审中-公开
标题翻译：与基于电阻的记忆有关的健康数据
公开(公告)号：US20160141029A1
公开(公告)日：2016-05-19
申请号：US14548205
申请日：2014-11-19
申请人： SANDISK TECHNOLOGIES INC.
发明人： ARIEL NAVON , IDAN ALROD , ERAN SHARON , IDAN GOLDENBERG , ALEXANDER BAZARSKY , TZ-YI LIU , TIANHONG YAN
IPC分类号： G11C13/00 , G11C29/02 , H01L21/66 , H01L45/00 , H01L27/24 , G06F3/06 , G11C29/50
CPC分类号： G11C13/0035 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C29/025 , G11C2013/0083 , G11C2029/0403 , G11C2029/4402 , G11C2213/71 , H01L22/14 , H01L27/2481
摘要： A method of fabricating a resistance-based memory includes initiating formation of a conductive path through a storage element of the resistance-based memory. The method further includes recording data of one or more parameters associated with the formation of the conductive path.
摘要翻译：一种制造基于电阻的存储器的方法包括：通过基于电阻的存储器的存储元件启动形成导电路径。该方法还包括记录与形成导电路径相关联的一个或多个参数的数据。

22. 发明授权

US09324943B2 Filamentary memory devices and methods 有权
标题翻译：遗迹记忆装置和方法
公开(公告)号：US09324943B2
公开(公告)日：2016-04-26
申请号：US14451179
申请日：2014-08-04
申请人： Micron Technology, Inc.
发明人： Lei Bi , Beth R. Cook , Marko Milojevic , Durai Vishak Nirmal Ramaswamy
IPC分类号： G11C11/00 , H01L45/00 , G11C13/00 , H01L27/24
CPC分类号： H01L45/08 , G11C13/0002 , G11C13/0007 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/35 , H01L27/2463 , H01L45/145
摘要： Apparatus, devices, systems, and methods are described that include filamentary memory cells. Mechanisms to substantially remove the filaments in the devices are described, so that the logical state of a memory cell that includes the removable filament can be detected. Additional apparatus, systems, and methods are described.
摘要翻译：描述了包括丝状记忆单元的装置，装置，系统和方法。描述了基本上去除器件中的细丝的机理，使得可以检测到包括可除去细丝的存储器单元的逻辑状态。描述了附加装置，系统和方法。

23. 发明申请

US20160111155A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND REWRITING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其优化方法
公开(公告)号：US20160111155A1
公开(公告)日：2016-04-21
申请号：US14979739
申请日：2015-12-28
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： YURIKO ISHITOBI , HITOSHI SUWA
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C11/1675 , G11C11/1677 , G11C13/0007 , G11C13/0023 , G11C13/0035 , G11C13/004 , G11C13/0064 , G11C2013/0073 , G11C2013/0076
摘要： A bitwise bidirectionally rewritable nonvolatile semiconductor storage device capable of performing a high-speed data rewrite, while enhancing endurance characteristics and data-retention characteristics of a memory cell. To achieve high-speed generation of rewrite-bit information indicating that a data rewrite is needed or not, the structure employs a logic circuit corresponding to the number of change patterns of write conditions and concurrently compares between read-out data RO of memory at the start of the data rewrite and prepared write data DIN. After an electrical data rewrite of the memory, the data rewrite is verified based on the rewrite-bit information stored in an internal buffer circuit. This protects an already-rewritten memory cell from unnecessary additional rewrite.
摘要翻译：一种能够进行高速数据重写的按位双向可重写非易失性半导体存储装置，同时提高存储单元的耐久性和数据保持特性。为了实现指示需要数据重写的重写位信息的高速生成，该结构采用与写入条件的变化模式的数量相对应的逻辑电路，并且同时在存储器的读出数据RO之间进行比较开始数据重写并准备写入数据DIN。在存储器的电气数据重写之后，基于存储在内部缓冲器电路中的重写位信息来验证数据重写。这样可以保护已经重写的内存单元免受不必要的额外重写。

24. 发明授权

US09312029B2 Memory device and associated controlling method 有权
标题翻译：存储器和相关控制方法
公开(公告)号：US09312029B2
公开(公告)日：2016-04-12
申请号：US14309920
申请日：2014-06-20
申请人： Macronix International Co., Ltd.
发明人： Win-San Khwa , Chao-I Wu , Tzu-Hsiang Su
IPC分类号： G11C11/56 , G11C29/12 , G11C29/50 , G11C29/04 , G11C13/00
CPC分类号： G11C29/12 , G11C11/5678 , G11C13/0004 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C29/50008 , G11C2013/0092 , G11C2029/0409 , G11C2211/563 , G11C2211/5644 , G11C2211/5646
摘要： A memory device and associated controlling method are provided. The memory device includes a memory cell array, a sensing unit and a controller. The memory cell array has a plurality of memory cells. The sensing unit is electrically connected to the memory cell array and the controller. The sensing unit senses characteristic of a memory cell of the plurality of memory cells. The controller determines whether the characteristic of the one of the memory cells deviates and accordingly controls the memory cell array.
摘要翻译：提供了存储器件和相关联的控制方法。存储器件包括存储单元阵列，感测单元和控制器。存储单元阵列具有多个存储单元。感测单元电连接到存储单元阵列和控制器。感测单元感测多个存储单元的存储单元的特性。控制器确定存储器单元之一的特性是否偏离，从而控制存储单元阵列。

25. 发明授权

US09311995B2 Semiconductor memory device and control method thereof 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US09311995B2
公开(公告)日：2016-04-12
申请号：US14306843
申请日：2014-06-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takamasa Okawa , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： G11C8/08 , G11C13/00 , G11C5/02 , H01L27/10 , G11C29/02 , G11C7/18 , G11C29/50
CPC分类号： G11C13/0035 , G11C5/02 , G11C7/18 , G11C13/0002 , G11C13/0026 , G11C29/024 , G11C2029/5006 , G11C2213/71 , H01L27/101
摘要： A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.
摘要翻译：一种半导体存储器件，包括：沿垂直于衬底的第一方向设置的第一线，并沿与衬底平行的第二方向延伸; 第二线沿第二方向设置并且被配置为在第一方向上延伸，第二线与第一线相交; 以及设置在第一线和第二线的交叉点处并且每个包括可变电阻元件的存储单元。此外，第三线在与第一和第二方向正交的第三方向上延伸。选择晶体管连接在第二和第三线之间。控制电路控制施加到第一和第三线以及选择晶体管的电压。控制电路使至少一个选择晶体管导通，从而检测在第三线中流动的电流，并根据检测结果确定选择晶体管的劣化状态。

26. 发明授权

US09275913B2 Memory arrays for both good data retention and low power operation 有权
标题翻译：存储器阵列，用于良好的数据保留和低功耗操作
公开(公告)号：US09275913B2
公开(公告)日：2016-03-01
申请号：US14133555
申请日：2013-12-18
申请人： Intermolecular, Inc.
发明人： Yun Wang , Imran Hashim
IPC分类号： H01L27/115 , H01L21/66 , G11C16/10 , G11C11/02 , H01L27/24 , G11C11/56 , H01L27/10 , H01L45/00 , G11C13/00
CPC分类号： H01L22/14 , G11C11/005 , G11C11/02 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0035 , G11C13/0069 , G11C16/10 , G11C2013/0071 , G11C2213/79 , H01L27/101 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/147
摘要： Designs and programming schemes can be used to form memory arrays having low power, high density and good data retention. High resistance interconnect lines can be used to partition the memory array can be partitioned into areas of high data retention and areas of low data retention. Variable gate voltages can be used in control transistors to store memory values having different data retention characteristics.
摘要翻译：可以使用设计和编程方案来形成具有低功率，高密度和良好数据保留的存储器阵列。高电阻互连线可用于分割存储阵列，可分为高数据保留区域和低数据保留区域。控制晶体管中可以使用可变栅极电压来存储具有不同数据保持特性的存储器值。

27. 发明授权

US09240235B2 Mitigating disturb effects for non-volatile memory 有权
标题翻译：减轻非易失性存储器的干扰效应
公开(公告)号：US09240235B2
公开(公告)日：2016-01-19
申请号：US14135294
申请日：2013-12-19
申请人： SANDISK TECHNOLOGIES INC.
发明人： Idan Alrod , Eran Sharon , Tz-Yi Liu , Tianhong Yan , Menahem Lasser
IPC分类号： G11C8/00 , G11C13/00
CPC分类号： G11C13/0033 , G11C13/0035 , G11C13/0069
摘要： A method includes adjusting a counter value to indicate an access operation to a first portion of a non-volatile memory. The access operation is an erase operation or a write operation. The adjusted counter value indicates that a number of access operations to the first portion have been performed since an access operation to a second portion of the non-volatile memory has been performed. The method also includes selectively initiating a remedial action to the second portion in response to a comparison of the number of access operations to a threshold.
摘要翻译：一种方法包括调整计数器值以指示对非易失性存储器的第一部分的访问操作。访问操作是擦除操作或写入操作。调整后的计数器值指示已经执行了对第一部分的访问操作的数量，因为已经执行了对非易失性存储器的第二部分的访问操作。该方法还包括响应于访问操作的数量与阈值的比较而选择性地启动对第二部分的补救动作。

28. 发明申请

US20160005463A1 RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY, AND OPERATING METHOD OF THE RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻记忆装置的电阻记忆装置，电阻记忆装置及操作方法
公开(公告)号：US20160005463A1
公开(公告)日：2016-01-07
申请号：US14697229
申请日：2015-04-27
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HYUN-KOOK PARK , YEONG-TAEK LEE , DAE-SEOK BYEON , YONG-KYU LEE , HYO-JIN KWON
IPC分类号： G11C13/00 , G11C29/08
CPC分类号： G11C13/0021 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2029/0407 , G11C2029/5006 , G11C2213/71
摘要： An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result, generating a control signal based on the measuring result, and adjusting a level of the bias control voltage in response to the control signal.
摘要翻译：电阻式存储器件的操作方法包括：对所述电阻式存储器件的存储单元阵列施加偏置控制电压，测量响应所施加的偏置控制电压而在所述存储单元阵列中发生的泄漏电流以产生测量结果，基于所述测量结果产生控制信号，以及响应于所述控制信号调整所述偏置控制电压的电平。

29. 发明授权

US09142290B2 Nonvolatile semiconductor device and method for driving same 有权
标题翻译：非易失性半导体器件及其驱动方法
公开(公告)号：US09142290B2
公开(公告)日：2015-09-22
申请号：US14078969
申请日：2013-11-13
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroshi Kanno , Yoichi Minemura , Takayuki Tsukamoto , Takamasa Okawa , Atsushi Yoshida
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0035 , G11C13/0064 , G11C13/0069
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including first wirings, second wirings, and a memory cell connected between the first wirings and the second wirings; and a control circuit unit configured to select a selected memory cell from the memory cells, perform a first operation of changing a resistance state of the selected memory cell between a first resistance state and a second resistance state, and determine whether the first operation has been properly performed or not and perform retry operation such as applying a retry pulse when the first operation has not been properly performed. The control circuit unit regards the selected memory cell as excessive retry operation and inhibits the selected memory cell in accordance with the number of times of the excessive retry operation when the number of times of the retry operation is over k times.
摘要翻译：根据一个实施例，非易失性存储器件包括：存储单元阵列，包括第一布线，第二布线和连接在第一布线和第二布线之间的存储单元; 以及控制电路单元，被配置为从存储单元中选择所选择的存储单元，执行在第一电阻状态和第二电阻状态之间改变所选存储单元的电阻状态的第一操作，并且确定第一操作是否已经正确执行，并且在第一操作未被正确执行时执行诸如应用重试脉冲的重试操作。控制电路单元将所选择的存储单元视为过度重试操作，并且当重试操作的次数超过k次时，根据过度重试操作的次数来禁止所选存储单元。

30. 发明申请

US20150187413A1 METHODS AND APPARATUSES USING A TRANSFER FUNCTION TO PREDICT RESISTANCE SHIFTS AND/OR NOISE OF RESISTANCE-BASED MEMORY 审中-公开
标题翻译：使用转移函数预测电阻变化和/或基于电阻的存储器的噪声的方法和装置
公开(公告)号：US20150187413A1
公开(公告)日：2015-07-02
申请号：US14595757
申请日：2015-01-13
申请人： Seagate Technology LLC
发明人： Ara Patapoutian , Ryan James Goss , Antoine Khoueir
IPC分类号： G11C13/00 , G11C11/56 , G11C29/08
CPC分类号： G11C13/0002 , G11C7/04 , G11C11/56 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C29/08 , G11C2013/0076
摘要： Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.
摘要翻译：测量影响基于电阻的非易失性存储器的存储单元的两个或多个工作负载指示器。两个或多个工作负载指示符被应用于响应于两个或更多个工作负载指示器预测电阻偏移和/或电阻噪声方差的传递函数。应用传递函数的结果来移位和/或确定用于影响存储器单元的程序操作和读取操作中的至少一个的阈值电阻。结果，存储单元的错误率降低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式