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1. 发明申请

US20150380086A1 RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻式存储器件和操作电阻式存储器件的方法
公开(公告)号：US20150380086A1
公开(公告)日：2015-12-31
申请号：US14695922
申请日：2015-04-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HYUN-KOOK PARK , YEONG-TAEK LEE , DAE-SEOK BYEON , YONG-KYU LEE , HYO-JIN KWON
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0064 , G11C2013/0045 , G11C2013/0066 , G11C2013/0073 , G11C2013/0076 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092
摘要： In operating a resistive memory device including a number of memory cells, a write pulse is applied to each of the plurality of memory cells such that each of the memory cells has a target resistance state between a first reference resistance and a second reference resistance higher than the first reference resistance. The resistance of each of the memory cells is read by applying a verify pulse to each of the plurality of memory cells. A verify write current pulse is applied to each of the memory cells that has resistance higher than the second reference resistance, and a verify write voltage pulse is applied to each of the memory cells that has resistance lower than the first reference resistance.
摘要翻译：在操作包括多个存储单元的电阻式存储器件时，将写入脉冲施加到多个存储器单元中的每一个，使得每个存储单元具有第一参考电阻和第二参考电阻之间的目标电阻状态，第一个参考电阻。通过对多个存储单元中的每一个应用验证脉冲来读取每个存储单元的电阻。将验证写入电流脉冲施加到具有高于第二参考电阻的电阻的每个存储器单元，并且将验证写电压脉冲施加到具有低于第一参考电阻的电阻的每个存储单元。

2. 发明申请

US20160035417A1 MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE 有权
标题翻译：存储器件和操作存储器件的方法
公开(公告)号：US20160035417A1
公开(公告)日：2016-02-04
申请号：US14698175
申请日：2015-04-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HYUN-KOOK PARK , YOUNG-HOON OH , DAE-SEOK BYEON , YONG-KYU LEE , HYO-JIN KWON
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G06F11/00 , G06F11/1048 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C2013/0045 , G11C2013/0054
摘要： A memory device and a method of operating the memory device are provided for performing a read-retry operation. The method of operating the memory device includes starting a read-retry mode, reading data of multiple cell regions using different read conditions, and setting a final read condition for the cell regions according to results of data determination operations on data read from the cell regions.
摘要翻译：提供了一种用于执行读取重试操作的存储器件和操作存储器件的方法。操作存储装置的方法包括开始读取重试模式，使用不同的读取条件读取多个单元区域的数据，并且根据从单元区域读取的数据的数据确定操作的结果来设置单元区域的最终读取条件。

3. 发明申请

US20140247645A1 NONVOLATILE MEMORY DEVICE AND RELATED METHOD FOR REDUCING ACCESS LATENCY 有权
标题翻译：非易失存储器件及相关方法，用于减少存取时间
公开(公告)号：US20140247645A1
公开(公告)日：2014-09-04
申请号：US14171849
申请日：2014-02-04
申请人： SAMSUNG ELECTRONICS CO., LTD.,
发明人： EUN-HYE PARK , HOI-JU CHUNG , YONG-JIN KWON , HYO-JIN KWON , YONG-JUN LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/0061 , G11C13/0002 , G11C13/004 , G11C2213/72
摘要： A nonvolatile memory device comprises a memory core comprising a plurality of variable resistance memory cells, an input/output (I/O) circuit configured to receive a first packet signal and a second packet signal in sequence, the first and second packet signals collectively comprising information for a memory access operation, and further configured to initiate a core access operation upon decoding the first packet signal and to selectively continue or discontinue the core access operation upon decoding the second packet signal, and a read circuit configured to perform part of the core access operation in response to the first packet signal before the second packet signal is decoded.
摘要翻译：非易失性存储器件包括存储器芯，其包括多个可变电阻存储器单元，输入/输出（I / O）电路被配置为依次接收第一分组信号和第二分组信号，第一和第二分组信号共同地包括用于存储器访问操作的信息，并且还被配置为在解码所述第一分组信号时发起核心访问操作，并且在解码所述第二分组信号时选择性地继续或中断所述核心访问操作;以及读取电路，被配置为执行所述核心的一部分在第二分组信号被解码之前响应于第一分组信号的接入操作。

4. 发明申请

US20160133323A1 MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US20160133323A1
公开(公告)日：2016-05-12
申请号：US14791636
申请日：2015-07-06
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HYO-JIN KWON , YEONG-TAEK LEE , DAE-SEOK BYEON
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/1673 , G11C11/56 , G11C13/0004 , G11C13/0007 , G11C2213/72
摘要： A method is for operating a memory device including a plurality of memory cells disposed in regions where a plurality of first signal lines and a plurality of second signal lines cross each other. The method includes applying an initial voltage to the plurality of first signal lines, floating the plurality of first signal lines to which the initial voltage is applied, applying a second inhibit voltage to the plurality of second signal lines, and increasing voltage levels of the plurality of first signal lines to a first inhibit voltage level via capacitive coupling between the plurality of first signal lines which are floated and the plurality of second signal lines to which the second inhibit voltage is applied.
摘要翻译：一种用于操作存储器件的方法，该存储器件包括设置在多个第一信号线和多条第二信号线彼此交叉的区域中的多个存储单元。该方法包括将初始电压施加到多个第一信号线，使施加有初始电压的多条第一信号线浮置，向多条第二信号线施加第二禁止电压，以及增加多个第一信号线的电压电平的第一信号线通过在浮置的多个第一信号线之间的电容耦合和施加第二禁止电压的多个第二信号线之间的第一禁止电压电平。

5. 发明申请

US20160093376A1 RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME TO REDUCE LEAKAGE CURRENT 有权
标题翻译：电阻式存储器件及其运行方法降低泄漏电流
公开(公告)号：US20160093376A1
公开(公告)日：2016-03-31
申请号：US14683269
申请日：2015-04-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： YONG-KYU LEE , DAE-SEOK BYEON , YEONG-TAEK LEE , CHI-WEON YOON , HYUN-KOOK PARK , HYO-JIN KWON
IPC分类号： G11C13/00
CPC分类号： G11C13/0023 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0078
摘要： A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.
摘要翻译：一种操作存储器件的方法包括从多个第一信号线中确定流过所选择的第一信号线的工作电流的值，所述第一信号线被施加选择电压; 将存储单元阵列划分为n个块，n是大于1的整数，基于工作电流的值; 以及将对应于n个块的具有不同电压电平的抑制电压施加到包括在n个块中的未选择的第二信号线。每个未选择的第二信号线是由于流过所选择的第一信号线的工作电流和由未选择的第二信号线和所选择的第一信号线寻址的存储器单元而引起的漏电流可能流过的通路。

6. 发明申请

US20160027510A1 MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US20160027510A1
公开(公告)日：2016-01-28
申请号：US14697244
申请日：2015-04-27
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： YONG-KYU LEE , DAE-SEOK BYEON , YEONG-TAEK LEE , CHI-WEON YOON , HYUN-KOOK PARK , HYO-JIN KWON
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0033 , G11C13/0035 , G11C16/10 , G11C2013/0092
摘要： A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.
摘要翻译：一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器根据执行编程循环的次数来改变多个存储单元之间的单元。响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平，连接到多个存储单元之间的未选择存储单元的第二信号线根据执行编程循环的次数而改变。

7. 发明申请

US20160118114A1 RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻式存储器件，电阻式存储器系统和操作电阻式存储器件的方法
公开(公告)号：US20160118114A1
公开(公告)日：2016-04-28
申请号：US14743488
申请日：2015-06-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HYO-JIN KWON , YEONG-TAEK LEE , DAE-SEOK BYEON
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1655 , G11C11/1657 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069
摘要： A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address.
摘要翻译：一种操作电阻式存储器件和包括电阻性存储器件的电阻式存储器系统的方法是用于包括多个位线和至少一个虚拟位线的电阻式存储器件。操作电阻式存储器件的方法包括检测伴随第一命令的第一地址，产生用于偏置非选择线路的多个禁止电压，以及向第一伪位线提供从多个禁止中选择的第一禁止电压基于检测到第一地址的结果的电压。

8. 发明申请

US20160005463A1 RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY, AND OPERATING METHOD OF THE RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻记忆装置的电阻记忆装置，电阻记忆装置及操作方法
公开(公告)号：US20160005463A1
公开(公告)日：2016-01-07
申请号：US14697229
申请日：2015-04-27
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HYUN-KOOK PARK , YEONG-TAEK LEE , DAE-SEOK BYEON , YONG-KYU LEE , HYO-JIN KWON
IPC分类号： G11C13/00 , G11C29/08
CPC分类号： G11C13/0021 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2029/0407 , G11C2029/5006 , G11C2213/71
摘要： An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result, generating a control signal based on the measuring result, and adjusting a level of the bias control voltage in response to the control signal.
摘要翻译：电阻式存储器件的操作方法包括：对所述电阻式存储器件的存储单元阵列施加偏置控制电压，测量响应所施加的偏置控制电压而在所述存储单元阵列中发生的泄漏电流以产生测量结果，基于所述测量结果产生控制信号，以及响应于所述控制信号调整所述偏置控制电压的电平。

9. 发明申请

US20150364188A1 MEMORY DEVICE READING AND CONTROL 有权
标题翻译：存储器件读取和控制
公开(公告)号：US20150364188A1
公开(公告)日：2015-12-17
申请号：US14661935
申请日：2015-03-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： YONG-KYU LEE , YEONG-TAEK LEE , DAE-SEOK BYEON , HYUN-KOOK PARK , HYO-JIN KWON
IPC分类号： G11C13/00 , G11C11/56
CPC分类号： G11C13/004 , G11C7/06 , G11C11/1673 , G11C11/56 , G11C11/5607 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C2013/0054 , G11C2213/71
摘要： A method of reading a memory device that includes a memory cell that stores data of at least two bits includes determining whether a cell resistance level is no greater than a threshold resistance level. If the cell resistance level is smaller than or equal to the threshold resistance level, then the data is read based on a first factor that is inversely proportional to the cell resistance level. If the cell resistance level is greater than the threshold resistance level, then the data is read based on a second factor that is proportional to the cell resistance level.
摘要翻译：一种读取存储器件的方法，该存储器件包括存储至少两个位的数据的存储器单元，包括确定单元电阻电平是否不大于阈值电阻电平。如果单元电阻电平小于或等于阈值电阻电平，则基于与单元电阻电平成反比的第一因子来读取数据。如果单元电阻电平大于阈值电阻电平，则基于与单元电阻电平成比例的第二因子来读取数据。

10. 发明申请

US20160042811A1 RESISTIVE MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：电阻式存储器件及其工作方法
公开(公告)号：US20160042811A1
公开(公告)日：2016-02-11
申请号：US14743521
申请日：2015-06-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HYO-JIN KWON , DAE-SEOK BYEON , YEONG-TAEK LEE , CHI-WEON YOON , YONG-KYU LEE , HYUN-KOOK PARK
IPC分类号： G11C29/00 , G11C29/44 , G11C13/00
CPC分类号： G11C29/76 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C13/0002 , G11C13/0023 , G11C13/0059 , G11C13/0064 , G11C13/0069 , G11C29/808 , G11C2029/4402 , G11C2213/71
摘要： A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
摘要翻译：电阻式存储器件包括存储单元阵列，其包括沿垂直方向堆叠的多个存储层。多个存储层中的每一个包括设置在多个第一线和多条第二线彼此交叉的区域中的多个存储单元。不良区域管理单元将包括来自多个存储器单元中的不良单元和至少一个第二存储器层的第一存储器层定义为不良区域。

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