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1. 发明授权

US09281345B2 Resistance change type memory device with three-dimensional structure 有权
标题翻译：具有三维结构的电阻变化型存储器件
公开(公告)号：US09281345B2
公开(公告)日：2016-03-08
申请号：US14107442
申请日：2013-12-16
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroshi Kanno , Yoichi Minemura , Takayuki Tsukamoto , Takamasa Okawa , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： H01L29/02 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/10 , H01L45/1226 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1675
摘要： According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.
摘要翻译：根据实施例，非易失性存储器件包括沿第一方向延伸的第一布线，沿与第一方向正交的第二方向延伸的第二布线。该设备包括第三布线，以及第一和第二存储器。第三配线在与第一方向交叉的第三方向上延伸并且与第二方向垂直，并且在第二布线的两侧沿第二方向对齐。第一存储器设置在第三布线对和第二布线中的一个之间，所述一对第三布线跨越第二布线彼此面对。第二存储器设置在第三布线对和第二布线中的另一个之间。第二布线具有与第一存储器接触的第一部分和与第二存储器接触的第二部分之间的块部分。

2. 发明申请

US20140347911A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20140347911A1
公开(公告)日：2014-11-27
申请号：US14023844
申请日：2013-09-11
申请人： Kabushiki Kaisha Toshiba
发明人： Yoichi Minemura , Takayuki Tsukamoto , Takamasa Okawa , Hiroshi Kanno , Atsushi Yoshida , Satoshi Konagai , Nobuaki Yasutake
IPC分类号： G11C13/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1˜100 Ω·cm.
摘要翻译：根据实施例的非易失性半导体存储器件包括存储单元块，其包括存储单元阵列，所述存储单元阵列包括：多个第一线; 与所述多个第一线相交的多个第二线; 以及存储单元，其设置在所述多个第一线和所述多条第二线的交点处，并且包括可变电阻元件，所述存储单元阵列还包括保护电阻膜，所述保护电阻膜分别设置在所述保护电阻膜的每个交点处多个第一线和多条第二线，并且与存储单元串联连接并与存储单元相接触，并且保护电阻膜由电阻率为1〜100Ω·cm的材料构成。

3. 发明授权

US09252358B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09252358B2
公开(公告)日：2016-02-02
申请号：US13767029
申请日：2013-02-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroshi Kanno , Takayuki Tsukamoto , Hiroyuki Fukumizu , Yoichi Minemura , Takamasa Okawa
IPC分类号： H01L21/332 , H01L29/06 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1206 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/16 , H01L45/1658
摘要： First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers is made larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, whereby the side wall layer adjacent to the first conductive layers is caused to function as the variable resistance element.
摘要翻译：首先，形成穿透第一导电层和层间绝缘层的沟槽。接下来，形成柱状导电层，以通过侧壁层填充沟槽。然后，在形成侧壁层之后，通过在侧壁层和第一导电层之间迁移氧原子或者在侧壁层和层间绝缘层之间迁移氧原子，侧壁中的氧原子的比例使与层间绝缘层相邻的层的厚度大于与第一导电层相邻的侧壁层中的氧原子的比例，由此使与第一导电层相邻的侧壁层起到可变电阻元件的作用。

4. 发明申请

US20150228337A1 SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20150228337A1
公开(公告)日：2015-08-13
申请号：US14306843
申请日：2014-06-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takamasa OKAWA , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： G11C13/00 , G11C5/02
CPC分类号： G11C13/0035 , G11C5/02 , G11C7/18 , G11C13/0002 , G11C13/0026 , G11C29/024 , G11C2029/5006 , G11C2213/71 , H01L27/101
摘要： A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.
摘要翻译：一种半导体存储器件，包括：沿垂直于衬底的第一方向设置的第一线，并沿与衬底平行的第二方向延伸; 第二线沿第二方向设置并且被配置为在第一方向上延伸，第二线与第一线相交; 以及设置在第一线和第二线的交叉点处并且每个包括可变电阻元件的存储单元。此外，第三线在与第一和第二方向正交的第三方向上延伸。选择晶体管连接在第二和第三线之间。控制电路控制施加到第一和第三线和选择晶体管的电压。控制电路使至少一个选择晶体管导通，从而检测在第三线中流动的电流，并根据检测结果确定选择晶体管的劣化状态。

5. 发明授权

US09397043B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09397043B1
公开(公告)日：2016-07-19
申请号：US14850444
申请日：2015-09-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoichi Minemura
IPC分类号： H01L29/792 , H01L23/528 , H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11575 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device according to an embodiment comprises a stacked body, the stacked body including a plurality of conductive layers disposed on a semiconductor substrate and an inter-layer insulating film disposed between the plurality of conductive layers. A columnar semiconductor layer is surrounded as a stacking direction of the stacked body. An isolation film extends from an outer surface of the stacked body to a bottom of the stacked body and has a longitudinal direction in a second direction. At least some of the isolation films include a base portion extending in the second direction and a terminal portion positioned at an end of the base portion, and a width of the end in a third direction intersecting the second direction is larger than a width of the base portion.
摘要翻译：根据实施例的半导体存储器件包括层叠体，所述层叠体包括设置在半导体衬底上的多个导电层和设置在所述多个导电层之间的层间绝缘膜。柱状半导体层作为层叠体的层叠方向被包围。隔离膜从层叠体的外表面延伸到层叠体的底部，并且在第二方向上具有纵向方向。至少一些隔离膜包括在第二方向上延伸的基部和位于基部的端部的端部，并且在与第二方向相交的第三方向上的端部的宽度大于基部。

6. 发明授权

US09368555B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09368555B2
公开(公告)日：2016-06-14
申请号：US14178636
申请日：2014-02-12
申请人： Kabushiki Kaisha Toshiba
发明人： Takamasa Okawa , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/249 , G11C13/0002 , G11C13/0026 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/2454 , H01L45/04 , H01L45/12 , H01L45/1226 , H01L45/146
摘要： This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.
摘要翻译：该半导体存储器件包括存储单元阵列，其包括：多个第一线; 与所述多个第一线相交的多个第二线; 多个存储单元，各自设置在所述多个第一线和所述多条第二线的交点处，并且包括可变电阻元件; 以及选择晶体管，其分别连接到所述多条第一线的端部。选择晶体管包括栅电极，栅极绝缘膜和导电层。此外，该导电层的一端连接到第一线的端部，并且由第一线和导电层之间连接由非线性材料构成的非线性电阻层。

7. 发明授权

US09286978B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09286978B2
公开(公告)日：2016-03-15
申请号：US14208242
申请日：2014-03-13
申请人： Kabushiki Kaisha Toshiba
发明人： Yoichi Minemura , Takayuki Tsukamoto , Takamasa Okawa , Hiroshi Kanno , Atsushi Yoshida
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value of the second resistance value distribution and a second lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value of the first resistance value distribution and a first lower limit value of the first resistance value distribution.
摘要翻译：根据实施例的非易失性半导体存储器件包括控制电路，其被配置为通过将存储单元设置为包括在电阻值分布中的一个中来使数据存储在存储单元中。控制电路被配置为设置第一电阻值分布和第二电阻值分布，第二电阻值分布具有比第一电阻值分布的电阻值大的电阻值，并且将第二宽度设定为大于第一电阻值分布宽度，第二宽度是第二电阻值分布的第二上限值和第二电阻值分布的第二下限值之间的宽度，第一宽度是第一电阻的第一上限值之间的宽度值分布和第一电阻值分布的第一下限值。

8. 发明授权

US09190147B2 Resistance changing memory with a first driver closer than a second driver 有权
标题翻译：电阻改变存储器，第一个驱动器比第二个驱动器更近
公开(公告)号：US09190147B2
公开(公告)日：2015-11-17
申请号：US13969835
申请日：2013-08-19
申请人： Kabushiki Kaisha Toshiba
发明人： Yoichi Minemura , Takayuki Tsukamoto , Hiroshi Kanno , Takamasa Okawa
IPC分类号： G11C7/12 , G11C8/08 , G11C13/00 , G11C5/02 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0002 , G11C5/025 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/1233
摘要： A memory cell array comprises memory cells disposed at intersections of a plurality of first lines disposed in parallel and a plurality of second lines disposed intersecting the first lines. The memory cell includes a variable resistance element.A set operation-dedicated first driver circuit, when executing on the memory cell a set operation for switching a memory cell from a high-resistance state to a low-resistance state, supplies a voltage to the first lines. A reset operation-dedicated first driver circuit, when executing on the memory cell a reset operation for switching the memory cell from a low-resistance state to a high-resistance state, supplies a voltage to the first lines.A length of a wiring line between the set operation-dedicated first driver circuit and the memory cell array is longer compared to a length of a wiring line between the reset operation-dedicated first driver circuit and the memory cell array.
摘要翻译：存储单元阵列包括设置在平行设置的多个第一线的交点处的存储单元和与第一线相交的多条第二线。存储单元包括可变电阻元件。一种设置的操作专用第一驱动器电路，当在存储器单元上执行用于将存储单元从高电阻状态切换到低电阻状态的设置操作时，向第一行提供电压。复位操作专用的第一驱动器电路当在存储器单元上执行用于将存储单元从低电阻状态切换到高电阻状态的复位操作时，向第一行提供电压。与设置的操作专用第一驱动器电路和存储单元阵列之间的布线的长度与复位操作专用第一驱动器电路和存储单元阵列之间的布线的长度相比更长。

9. 发明申请

US20140061577A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20140061577A1
公开(公告)日：2014-03-06
申请号：US13767029
申请日：2013-02-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroshi KANNO , Takayuki Tsukamoto , Hiroyuki Fukumizu , Yoichi Minemura , Takamasa Okawa
IPC分类号： H01L45/00
CPC分类号： H01L45/1206 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/16 , H01L45/1658
摘要： First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers is made larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, whereby the side wall layer adjacent to the first conductive layers is caused to function as the variable resistance element.
摘要翻译：首先，形成穿透第一导电层和层间绝缘层的沟槽。接下来，形成柱状导电层，以通过侧壁层填充沟槽。然后，在形成侧壁层之后，通过在侧壁层和第一导电层之间迁移氧原子或者在侧壁层和层间绝缘层之间迁移氧原子，侧壁中的氧原子的比例使与层间绝缘层相邻的层的厚度大于与第一导电层相邻的侧壁层中的氧原子的比例，由此使与第一导电层相邻的侧壁层起到可变电阻元件的作用。

10. 发明授权

US09224469B2 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US09224469B2
公开(公告)日：2015-12-29
申请号：US14305503
申请日：2014-06-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoichi Minemura , Takayuki Tsukamoto , Hiroshi Kanno , Takamasa Okawa , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C2013/0054 , G11C2013/0076 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79
摘要： A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes first lines and second lines intersecting each other, a third line commonly connecting to the first lines, memory cells disposed at intersections of the first lines and the second lines, respectively. The control circuit is configured to execute a state determining operation detecting a voltage of the third line, and adjust a voltage applied to the first lines and the second lines during a resetting operation or a setting operation based on a result of the state determining operation. The resetting operation raises a resistance value of the variable resistance element. The setting operation lowers the resistance value of the variable resistance element.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括彼此相交的第一行和第二行，通常连接到第一行的第三行，分别设置在第一行和第二行的交叉处的存储单元。控制电路被配置为执行检测第三线的电压的状态确定操作，并且在基于状态确定操作的结果的复位操作或设置操作期间调整施加到第一线路和第二线路的电压。复位操作提高了可变电阻元件的电阻值。设定动作降低可变电阻元件的电阻值。

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