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21. 发明申请

US20170052788A1 FUSIBLE INSTRUCTIONS AND LOGIC TO PROVIDE OR-TEST AND AND-TEST FUNCTIONALITY USING MULTIPLE TEST SOURCES 审中-公开
标题翻译：使用多个测试源提供可靠的说明和逻辑提供测试和测试功能
公开(公告)号：US20170052788A1
公开(公告)日：2017-02-23
申请号：US15340916
申请日：2016-11-01
申请人： Intel Corporation
发明人： MAXIM LOKTYUKHIN , ROBERT VALENTINE , JULIAN C. HORN , MARK J. CHARNEY
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3822 , G06F9/30029 , G06F9/30058 , G06F9/30094 , G06F9/3836
摘要： Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.
摘要翻译：易熔指令和逻辑在多个测试源上提供OR测试和与测试功能。一些实施例包括解码用于执行的测试指令的处理器解码级，指定第一，第二和第三源数据操作数的指令以及操作类型。执行单元响应于解码的测试指令，根据指定的操作类型在来自第一和第二源数据操作数的数据之间执行一个逻辑操作，并且执行来自第三源数据操作数的数据和第一个逻辑运算结果设置条件标志。一些实施例通过将一个逻辑指令与现有技术的测试指令进行融合来动态地产生测试指令。其他实施例通过即时编译器生成测试指令。一些实施例还将测试指令与随后的条件分支指令融合，并且根据条件标志的设置来执行分支。

22. 发明申请

US20170024212A1 HARDWARE ACCELERATION COMPONENTS FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS 审中-公开
标题翻译：硬件加速组件用于将用户说明转换为本指令
公开(公告)号：US20170024212A1
公开(公告)日：2017-01-26
申请号：US15042005
申请日：2016-02-11
申请人： Soft Machines, Inc.
发明人： Mohammad ABDALLAH
IPC分类号： G06F9/30 , G06F12/0875 , G06F9/455
CPC分类号： G06F9/30174 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30098 , G06F9/30189 , G06F9/3802 , G06F9/3814 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3861 , G06F9/3863 , G06F9/3867 , G06F9/3879 , G06F9/45516 , G06F12/0875 , G06F15/8007 , G06F2212/452
摘要： A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.
摘要翻译：一种基于硬件的翻译加速器。硬件包括用于访问访客指令的访客提取逻辑组件; 耦合到客户提取逻辑组件的访客提取缓冲器和用于将访客指令组装到访客指令块中的分支预测组件; 以及耦合到访客提取缓冲器的转换表，用于将访客指令块转换为相应的本机转换块。硬件还包括耦合到用于存储对应的本机转换块的转换表的本地高速缓存，以及耦合到本地高速缓存的转换看待缓冲器，用于存储客户指令块到对应的本机转换块的映射，其中在随后的请求访客指令，转换看待缓冲区被索引以确定是否发生命中，其中映射指示客户指令在本机高速缓存中具有对应的转换的本地指令。

23. 发明申请

US20160378473A1 INSTRUCTION AND LOGIC FOR CHARACTERIZATION OF DATA ACCESS 有权
标题翻译：数据访问特征的指令和逻辑
公开(公告)号：US20160378473A1
公开(公告)日：2016-12-29
申请号：US14752014
申请日：2015-06-26
申请人： Intel Corporation
发明人： Kshitij A. Doshi , Christopher J. Hughes
IPC分类号： G06F9/30 , G06F12/08 , G06T1/20
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/3836 , G06F12/1027 , G06F12/1045 , G06F2201/885 , G06F2212/452 , G06F2212/68
摘要： A processor includes a front end to receive an instruction, a decoder to decode the instruction, a core to execute the first instruction, and a retirement unit to retire the first instruction. The core includes logic to execute the first instruction, including logic to repeatedly record a translation lookaside buffer (TLB) until a designated number of records are determined, and flush the TLB after a flush interval.
摘要翻译：处理器包括用于接收指令的前端，解码指令的解码器，执行第一指令的核心以及退出第一指令的退出单元。核心包括执行第一指令的逻辑，包括重复记录翻译后备缓冲器（TLB）直到确定指定数量的记录的逻辑，并且在刷新间隔之后刷新TLB。

24. 发明申请

US20160283242A1 APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION 审中-公开
标题翻译：矢量水平逻辑指导的装置和方法
公开(公告)号：US20160283242A1
公开(公告)日：2016-09-29
申请号：US14582170
申请日：2014-12-23
申请人： Intel Corporation
发明人： Elmoustapha OULD-AHMED-VALL , David GUILLEN FANDOS , Jesus F. SANCHEZ , Guillem SOLE , Roger ESPASA
IPC分类号： G06F9/38 , G06F12/08 , G06F9/30
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30167 , G06F9/34
摘要： An apparatus and method are described for performing vector horizontal logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory, and execution logic to determine a value of a first set of one or more data elements from a first specified set of bits of an immediate operand, wherein positions of the first set of one or more data elements determined from the first specified set of bits of the immediate operand are based on a first set of one or more index values that have a most significant bit corresponding to a packed data element at a first set of one or more positions of a destination packed data operand and that have a least significant bit corresponding to a data element at a corresponding position of a first source packed data operand.
摘要翻译：描述了用于执行向量水平逻辑指令的装置和方法。例如，处理器的一个实施例包括：从存储器取出指令的提取逻辑，以及执行逻辑，用于从立即操作数的第一指定位组确定一个或多个数据元素的第一集合的值，其中位置从所述立即数操作数的所述第一指定位组确定的所述第一组一个或多个数据元素是基于一个或多个索引值的第一集合，所述索引值具有与第一集合上的打包数据元素相对应的最高有效位目的地打包数据操作数的一个或多个位置，并且具有对应于第一源打包数据操作数的对应位置处的数据元素的最低有效位。

25. 发明授权

US09405537B2 Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm 有权
标题翻译：用于计算多轮skein散列算法的执行单元的装置和方法
公开(公告)号：US09405537B2
公开(公告)日：2016-08-02
申请号：US13997186
申请日：2011-12-22
申请人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Erdinc Ozturk , Vinodh Gopal , Wajdi K. Feghali , Sean M. Gulley , Martin G. Dixon
发明人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Erdinc Ozturk , Vinodh Gopal , Wajdi K. Feghali , Sean M. Gulley , Martin G. Dixon
IPC分类号： G06F9/30 , H04L9/06 , G06F9/38
CPC分类号： G06F9/30029 , G06F9/30007 , G06F9/30018 , G06F9/30036 , G06F9/3885 , G06F9/3895 , H04L9/0643
摘要： An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.
摘要翻译：描述了包括指令流水线内的执行单元的装置。执行单元具有包括a）和b）的电路的多个级，如下所述。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四进制字的第一输入和用于接收第二四字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

26. 发明授权

US09355363B2 Systems and methods for virtual parallel computing using matrix product states 有权
标题翻译：使用矩阵产品状态的虚拟并行计算的系统和方法
公开(公告)号：US09355363B2
公开(公告)日：2016-05-31
申请号：US13762278
申请日：2013-02-07
申请人： TRUSTEES OF BOSTON UNIVERSITY , UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
发明人： Claudio Chamon , Eduardo R. Mucciolo
IPC分类号： G06N99/00 , G06F17/16 , B82Y10/00 , G06F9/30
CPC分类号： G06N99/002 , B82Y10/00 , G06F9/30029 , G06F17/16
摘要： A virtual parallel computing system and method represents bits with matrices and computes over all input states in parallel through a sequence of matrix operations. The matrix operations relate to logic gate operators to carry out a function implementation that represents a problem to be solved. Initial matrices are prepared to encode the weights of all input states, which can be binary states. Intermediate results can be simplified to decrease computational complexity while maintaining useful approximation results. The final matrices can encode the answer(s) to the problem represented by the function implementation. The system and method are particularly useful in speeding up database searches and in counting solutions of satisfiability problems.
摘要翻译：虚拟并行计算系统和方法表示具有矩阵的位，并通过矩阵运算序列并行计算所有输入状态。矩阵运算涉及逻辑门操作符，以执行表示要解决的问题的函数实现。准备初始矩阵以对可以是二进制状态的所有输入状态的权重进行编码。可以简化中间结果以减少计算复杂度，同时保持有用的近似结果。最终的矩阵可以将函数编码到由函数实现表示的问题中。该系统和方法在加速数据库搜索和计算可满足性问题的解决方案中特别有用。

27. 发明授权

US09239702B2 Data processing apparatus 有权
标题翻译：数据处理装置
公开(公告)号：US09239702B2
公开(公告)日：2016-01-19
申请号：US11570167
申请日：2005-06-08
申请人： Antonius Adrianus Maria Van Wel
发明人： Antonius Adrianus Maria Van Wel
IPC分类号： G06F5/01 , G06F5/00 , G06F7/76 , G06F9/30 , H04N19/184 , H04N19/169 , H04N19/42 , H04N19/436 , H04B1/66 , G06F5/16
CPC分类号： G06F5/01 , G06F5/00 , G06F5/015 , G06F5/16 , G06F7/76 , G06F7/762 , G06F7/768 , G06F9/30018 , G06F9/30029 , G06F9/30036 , H04B1/66 , H04B1/667 , H04N19/184 , H04N19/1883 , H04N19/42 , H04N19/436
摘要： A programmable data processing apparatus having a bit-plane extraction operation is described, for extracting data from a value of, for example, 32 bits containing 4 bytes, 1a to 1d. Each byte 1a to 1d comprises 8 bits, (a0-a7, b0-b7, c0-c7 and d0-d7, respectively). The bit-plane extraction operation retrieves one bit from each of these bytes, for example the second bit (a1, b1, c1, d1), which is specified by an argument. The operation involves concatenating these bits (a1, b1, c1, d1) and returning a result value 5. Depending on the particular data processing application, the result value may be bit-reversed to provide a result value 7 (for example, if a bit-reversal is required to deal with endianness, or other reasons). The bit-plane extraction operation can be used as a pre-processing operation in data processing operations such as “sum-of-absolute-differences” in the processing of video data.
摘要翻译：描述了具有位平面提取操作的可编程数据处理装置，用于从例如包含4字节的数据的1a，1d到1d的值提取数据。每个字节1a至1d包括8位（分别为a0-a7，b0-b7，c0-c7和d0-d7）。位平面提取操作从这些字节中的每一个中检索一位，例如由参数指定的第二位（a1，b1，c1，d1）。该操作涉及连接这些位（a1，b1，c1，d1）并返回结果值5.根据特定的数据处理应用，结果值可以被比特反转以提供结果值7（例如，如果a 需要位反转以处理字节或其他原因）。位图提取操作可以用作数据处理操作中的预处理操作，诸如视频数据处理中的“绝对差之和”。

28. 发明授权

US09218182B2 Systems, apparatuses, and methods for performing a shuffle and operation (shuffle-op) 有权
标题翻译：用于执行洗牌和操作的系统，设备和方法（随机播放）
公开(公告)号：US09218182B2
公开(公告)日：2015-12-22
申请号：US13539116
申请日：2012-06-29
申请人： Igor Ermolaev , Elmoustapha Ould-Ahmed-Vall , Bret Toll , Jesus Corbal , Andrey Naraikin
发明人： Igor Ermolaev , Elmoustapha Ould-Ahmed-Vall , Bret Toll , Jesus Corbal , Andrey Naraikin
IPC分类号： G06F3/00 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30098 , G06F9/30145 , G06F9/3016
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor a data element shuffle and an operation on the shuffled data elements in response to a single data element shuffle and an operation instruction that includes a destination vector register operand, a first and second source vector register operands, an immediate value, and an opcode are described.
摘要翻译：用于在计算机处理器中响应于单个数据元素随机播放的数据元素随机播放和对混洗数据元素的操作的系统，装置和方法的实施例，以及包括目的地向量寄存器操作数，第一和第二描述源向量寄存器操作数，立即值和操作码。

29. 发明授权

US09135004B2 Rotate then operate on selected bits facility and instructions therefor 有权
标题翻译：旋转然后根据选定的位设备和指令进行操作
公开(公告)号：US09135004B2
公开(公告)日：2015-09-15
申请号：US14484323
申请日：2014-09-12
申请人： International Business Machines Corporation
发明人： Dan F. Greiner , Timothy J. Slegel , Joachim von Buttlar
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/30189 , G06F9/342
摘要： A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
摘要翻译：旋转，然后操作具有T位的指令被执行，其中第一寄存器中的第一操作数旋转一个量，并且对旋转的第一操作数的选定部分执行布尔运算，并且在第二寄存器中执行第二操作数。如果T位为“0”，则将布尔运算结果的选定部分插入到第二寄存器的第二个操作数的相应位中。如果T位为“1”，除了插入的位之外，所转动的第一个操作数的选定部分以外的其他位被保存在第二个寄存器中。

30. 发明申请

US20150212816A1 METHOD AND APPARATUS FOR PERFORMING LOGICAL COMPARE OPERATIONS 审中-公开
标题翻译：用于执行逻辑操作的方法和装置
公开(公告)号：US20150212816A1
公开(公告)日：2015-07-30
申请号：US14684412
申请日：2015-04-12
申请人： Intel Corporation
发明人： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
摘要： A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
摘要翻译：一种用于在处理器中包括用于对打包或未打包的数据执行逻辑比较和分支支持操作的指令的方法和装置。在一个实施例中，指令解码逻辑解码用于执行单元对包括逻辑比较的打包数据元素进行操作的指令。包括128位打包数据寄存器的寄存器文件存储打包的单精度浮点数（SPFP）和压缩整数数据元素。逻辑比较可以包括SPFP数据元素的比较和整数数据元素的比较，并且设置至少一个位以指示结果。基于这些比较，采取分支支持行动。这种分支支持动作可以包括设置至少一个比特，响应于分支指令又可以由分支单元利用该比特。或者，分支支持动作可以包括分支到指示的目标代码位置。

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