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21. 发明授权

US08429355B2 Information processor system 失效
公开(公告)号：US08429355B2
公开(公告)日：2013-04-23
申请号：US12962753
申请日：2010-12-08
申请人： Seiji Miura
发明人： Seiji Miura
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F5/12 , G06F13/1663 , G06F13/1673
摘要： In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.

22. 发明申请

US20110296063A1 BUFFER MANAGER AND METHODS FOR MANAGING MEMORY 有权
标题翻译：缓存管理器和管理存储器的方法
公开(公告)号：US20110296063A1
公开(公告)日：2011-12-01
申请号：US13038266
申请日：2011-03-01
申请人： Alon Pais , Nafea Bishara
发明人： Alon Pais , Nafea Bishara
IPC分类号： G06F5/14
CPC分类号： H04L47/621 , G06F5/12 , G06F2205/106
摘要： Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种方法，包括：在芯片上系统（SOC）中管理多个缓冲器地址; 并且如果SOC中的多个可用缓冲器地址低于低阈值，则从SOC外部的存储器获得一个或多个缓冲器地址到SOC。还描述和要求保护其他实施例。

23. 发明申请

US20110276731A1 DUAL-PORT FUNCTIONALITY FOR A SINGLE-PORT CELL MEMORY DEVICE 审中-公开
标题翻译：单端口单元存储器件的双端口功能
公开(公告)号：US20110276731A1
公开(公告)日：2011-11-10
申请号：US13185255
申请日：2011-07-18
申请人： Heyun Howard Liu
发明人： Heyun Howard Liu
IPC分类号： G06F5/14
CPC分类号： G06F5/12 , G06F5/10 , G06F2205/108 , G06F2205/123 , H04L49/90 , H04L49/9089
摘要： A network node (5) including a line card (20) for packet-based data communications is disclosed. The line card (20) includes a transmit FIFO buffer (24T) and a receive FIFO buffer (24R), for buffering communications within the line card (20). Each of the buffers (24T, 24R) operate in a dual-port fashion, receiving asynchronous read and write requests, for reading data words from and writing data words to the buffers (24T, 24R). The buffers (24T, 24R) each include a memory array (45) of conventional single port random access memory cells, for example static RAM cells. Clock cycles are assigned by the buffers (24T, 24R) as internal read and internal write cycles, in alternating fashion. A write buffer (42) receives input data words, and schedules a double-data-word write to the memory array (45) upon receiving a pair of input data words, in the next internal write cycle. A read request buffer (44) receives read strobes, or read enable signals, from a downstream function, and upon receiving two such strobes, schedules the read of a double-data-word from the memory array (45). By converting the asynchronous read and write requests into scheduled reads and writes, respectively, the buffers (24T, 24R) operate as dual-port FIFO buffers.
摘要翻译：公开了一种包括用于基于分组的数据通信的线路卡（20）的网络节点（5）。线卡（20）包括发送FIFO缓冲器（24T）和接收FIFO缓冲器（24R），用于缓冲线卡（20）内的通信。每个缓冲器（24T，24R）以双端口方式工作，接收异步读和写请求，用于从缓冲器（24T，24R）读取数据字并将数据字写入缓冲器（24T，24R）。缓冲器（24T，24R）各自包括常规单端口随机存取存储器单元的存储器阵列（45），例如静态RAM单元。时钟周期由缓冲器（24T，24R）分配为内部读和内部写周期，以交替方式。写入缓冲器（42）接收输入数据字，并且在下一个内部写周期中接收到一对输入数据字后，对存储器阵列（45）进行双数据字写入。读取请求缓冲器（44）从下游功能接收读取选通信号或读取使能信号，并且在接收到两个这样的选通信号时，从存储器阵列（45）调度双数据字的读取。通过将异步读取和写入请求分别转换为预定的读取和写入，缓冲器（24T，24R）作为双端口FIFO缓冲器运行。

24. 发明申请

US20110238872A1 Disk Drive System On Chip With Integrated Buffer Memory and Support for Host Memory Access 有权
标题翻译：磁盘驱动系统片上集成缓冲内存和支持主机内存访问
公开(公告)号：US20110238872A1
公开(公告)日：2011-09-29
申请号：US13154356
申请日：2011-06-06
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G06F5/14
CPC分类号： G06F5/12 , G06F3/0613 , G06F3/0656 , G06F3/0676 , G11B20/10527 , G11B2020/10675
摘要： A circuit for a storage device that communicates with a host device comprises a first high speed interface. A storage controller communicates with the high speed interface. A buffer communicates with the storage controller. The storage device generates storage buffer data during operation. The storage controller is adapted to selectively store the storage buffer data in at least one of the buffer and/or in the host device via the high speed interface. A bridge chip for enterprise applications couples the circuit to an enterprise device.
摘要翻译：用于与主机设备通信的存储设备的电路包括第一高速接口。存储控制器与高速接口通信。缓冲区与存储控制器通信。存储设备在操作期间生成存储缓冲区数据。存储控制器适于经由高速接口选择性地将存储缓冲器数据存储在缓冲器和/或主机设备中的至少一个中。用于企业应用的桥芯片将电路耦合到企业设备。

25. 发明授权

US07984209B1 Data interface methods and circuitry with reduced latency 有权
标题翻译：具有降低延迟的数据接口方法和电路
公开(公告)号：US07984209B1
公开(公告)日：2011-07-19
申请号：US11638150
申请日：2006-12-12
申请人： Vinson Chan , Michael Menghui Zheng , Chong H. Lee
发明人： Vinson Chan , Michael Menghui Zheng , Chong H. Lee
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F5/12 , G06F2205/126
摘要： Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.
摘要翻译：用于在可能具有一些不同速度的两种不同时钟制式之间对数据进行接口的接口电路包括确定哪个时钟方案更快的能力。根据哪个时钟状态被发现更快，基线（数据写入和接口电路中的FIFO存储器的数据读取地址之间的标称差）被移位（即，朝向FIFO的满或空状态，如适用的那样）为什么时钟制度被发现是更快）。还可以对用于诸如字符插入/删除和溢出/下溢指示的目的的阈值进行调整。该技术可以允许使用较小的FIFO并减少接口电路的延迟。

26. 发明申请

US20100091399A1 ARCHITECTURE FOR DATA STORAGE SYSTEMS 有权
标题翻译：数据存储系统的架构
公开(公告)号：US20100091399A1
公开(公告)日：2010-04-15
申请号：US12579678
申请日：2009-10-15
申请人： Tony Yoon , Siu-Hung Fred Au
发明人： Tony Yoon , Siu-Hung Fred Au
IPC分类号： G11B5/02
CPC分类号： G06F5/12 , G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/1673
摘要： A system includes N first-in first-out (FIFO) modules, a buffer manager module, and N input/output (I/O) modules, where N is an integer greater than 1. The buffer manager module retrieves a set of N data units from a buffer and outputs the set of N data units to the N FIFO modules in parallel at a time, respectively. The N I/O modules receive the set of N data units from the N FIFOs in parallel, respectively, and output the N data units to a medium.
摘要翻译：系统包括N个先进先出（FIFO）模块，缓冲管理器模块和N个输入/输出（I / O）模块，其中N是大于1的整数。缓冲管理器模块检索一组N 数据单元，并将N组数据单元一次并行输出到N个FIFO模块。 N I / O模块分别从N个FIFO并行接收一组N个数据单元，并将N个数据单元输出到介质。

27. 发明申请

US20090271544A1 APPARATUS AND METHOD FOR WRITING DATA TO RECORDING MEDIUM 有权
标题翻译：用于将数据写入记录介质的装置和方法
公开(公告)号：US20090271544A1
公开(公告)日：2009-10-29
申请号：US12420631
申请日：2009-04-08
申请人： Yutaka Oishi
发明人： Yutaka Oishi
IPC分类号： G06F5/00
CPC分类号： G06F3/0656 , G06F3/0613 , G06F3/0673 , G06F5/12
摘要： A distance calculating unit calculates a distance from a current position on a tape to the end of the tape. A command processing unit receives a write command. If the distance is small, a determining unit sets a usable capacity of a buffer to be equal to a maximum capacity of the buffer. If the distance is large, the determining unit sets the usable capacity of the buffer according to the distance. If a capacity for data indicated by the write command is less than or equal to a difference between the usable capacity and current usage of the buffer, a buffer managing unit stores the data in the buffer. When the command processing unit receives a write FM command, the buffer managing unit reads the data from the buffer, updates the current usage, and a channel input/output unit writes the data to the tape.
摘要翻译：距离计算单元计算从磁带上的当前位置到磁带末端的距离。命令处理单元接收写命令。如果距离小，则确定单元将缓冲器的可用容量设置为等于缓冲器的最大容量。如果距离较大，则确定单元根据距离设定缓冲器的可用容量。如果由写命令指示的数据容量小于或等于缓冲器的可用容量和当前使用量之间的差异，则缓冲器管理单元将数据存储在缓冲器中。当命令处理单元接收到写入FM命令时，缓冲器管理单元从缓冲器读取数据，更新当前使用，并且通道输入/输出单元将数据写入磁带。

28. 发明授权

US07594048B1 Determining transit time across an asynchronous FIFO memory by measuring fractional occupancy 有权
$Determining transit time across an asynchronous FIFO memory by measuring fractional occupancy$
标题翻译：通过测量分数占用来确定跨异步FIFO存储器的传输时间
公开(公告)号：US07594048B1
公开(公告)日：2009-09-22
申请号：US11893004
申请日：2007-08-14
申请人： Gareth David Edwards , David Finlay Taylor , Duncan Andrew Cockburn , Douglas Michael Grant , Stuart Alan Nisbet
发明人： Gareth David Edwards , David Finlay Taylor , Duncan Andrew Cockburn , Douglas Michael Grant , Stuart Alan Nisbet
IPC分类号： G06F3/00
CPC分类号： G06F5/12
摘要： Measuring transit time across an asynchronous first-in-first-out (FIFO) memory can include sampling an indication of a value of a read pointer of the FIFO memory at a sampling frequency that exceeds a frequency of a read clock and a write clock of the FIFO memory. An indication of a value of a write pointer of the FIFO memory can be sampled at the sampling frequency. For each sampling period, a measure of occupancy of the FIFO memory can be calculated according to a sampled pair including the indication of the value of the read pointer and the indication of the value of the write pointer. The measure of occupancy can be averaged over a predetermined number of cycles of the sampling frequency. The averaged measure of occupancy can be output as an indication of transit time across the FIFO memory.
摘要翻译：跨越异步先入先出（FIFO）存储器测量传输时间可以包括以超过读取时钟的频率和读取时钟的采样频率对FIFO存储器的读指针的值的指示进行采样 FIFO存储器。可以以采样频率对FIFO存储器的写指针的值的指示进行采样。对于每个采样周期，可以根据包括读指针的值的指示和写指针的值的指示的采样对来计算FIFO存储器的占用量。可以在采样频率的预定数量的周期内对占用的量度进行平均。可以将占用的平均度量输出为FIFO存储器上的传输时间的指示。

29. 发明授权

US07477649B2 Active FIFO threshold adjustment 有权
标题翻译：活动FIFO阈值调整
公开(公告)号：US07477649B2
公开(公告)日：2009-01-13
申请号：US10196824
申请日：2002-07-17
申请人： Christopher D. Paulson , Timothy D. Thompson , Steven A. Schauer
发明人： Christopher D. Paulson , Timothy D. Thompson , Steven A. Schauer
IPC分类号： H04L12/28
CPC分类号： G06F5/12 , G06F2205/126 , H04L47/266 , H04L47/30 , H04L49/90 , H04L49/901
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to store input data in response to a write pointer and present output data in response to a read pointer. The second circuit may be configured to generate a control signal in response to the write pointer, the read pointer and a type of an information packet containing the input data.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为响应于写指针存储输入数据，并且响应于读指针而呈现输出数据。第二电路可以被配置为响应于写指针，读指针和包含输入数据的信息分组的类型来生成控制信号。

30. 发明授权

US07457892B2 Data communication flow control device and methods thereof 有权
公开(公告)号：US07457892B2
公开(公告)日：2008-11-25
申请号：US11446891
申请日：2006-06-05
申请人： James E. Innis , Iftekhar Ahmed , Matthew Joseph Taylor , David W. Todd
发明人： James E. Innis , Iftekhar Ahmed , Matthew Joseph Taylor , David W. Todd
IPC分类号： G06F3/00
CPC分类号： G06F5/12 , G06F2205/126
摘要： A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

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