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1. 发明申请

US20110276731A1 DUAL-PORT FUNCTIONALITY FOR A SINGLE-PORT CELL MEMORY DEVICE 审中-公开
标题翻译：单端口单元存储器件的双端口功能
公开(公告)号：US20110276731A1
公开(公告)日：2011-11-10
申请号：US13185255
申请日：2011-07-18
申请人： Heyun Howard Liu
发明人： Heyun Howard Liu
IPC分类号： G06F5/14
CPC分类号： G06F5/12 , G06F5/10 , G06F2205/108 , G06F2205/123 , H04L49/90 , H04L49/9089
摘要： A network node (5) including a line card (20) for packet-based data communications is disclosed. The line card (20) includes a transmit FIFO buffer (24T) and a receive FIFO buffer (24R), for buffering communications within the line card (20). Each of the buffers (24T, 24R) operate in a dual-port fashion, receiving asynchronous read and write requests, for reading data words from and writing data words to the buffers (24T, 24R). The buffers (24T, 24R) each include a memory array (45) of conventional single port random access memory cells, for example static RAM cells. Clock cycles are assigned by the buffers (24T, 24R) as internal read and internal write cycles, in alternating fashion. A write buffer (42) receives input data words, and schedules a double-data-word write to the memory array (45) upon receiving a pair of input data words, in the next internal write cycle. A read request buffer (44) receives read strobes, or read enable signals, from a downstream function, and upon receiving two such strobes, schedules the read of a double-data-word from the memory array (45). By converting the asynchronous read and write requests into scheduled reads and writes, respectively, the buffers (24T, 24R) operate as dual-port FIFO buffers.
摘要翻译：公开了一种包括用于基于分组的数据通信的线路卡（20）的网络节点（5）。线卡（20）包括发送FIFO缓冲器（24T）和接收FIFO缓冲器（24R），用于缓冲线卡（20）内的通信。每个缓冲器（24T，24R）以双端口方式工作，接收异步读和写请求，用于从缓冲器（24T，24R）读取数据字并将数据字写入缓冲器（24T，24R）。缓冲器（24T，24R）各自包括常规单端口随机存取存储器单元的存储器阵列（45），例如静态RAM单元。时钟周期由缓冲器（24T，24R）分配为内部读和内部写周期，以交替方式。写入缓冲器（42）接收输入数据字，并且在下一个内部写周期中接收到一对输入数据字后，对存储器阵列（45）进行双数据字写入。读取请求缓冲器（44）从下游功能接收读取选通信号或读取使能信号，并且在接收到两个这样的选通信号时，从存储器阵列（45）调度双数据字的读取。通过将异步读取和写入请求分别转换为预定的读取和写入，缓冲器（24T，24R）作为双端口FIFO缓冲器运行。

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