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21. 发明申请

US20020013873A1 Data-processing unit with a circuit arrangement for connecting a first communications bus with a second communications bus 有权
标题翻译：具有用于将第一通信总线与第二通信总线连接的电路装置的数据处理单元
公开(公告)号：US20020013873A1
公开(公告)日：2002-01-31
申请号：US09835138
申请日：2001-04-16
申请人： Fujitsu Siemens Computers GmbH
发明人： Nikolaus Demharter , Andreas Knoepfle
IPC分类号： G06F013/38
CPC分类号： G06F13/4054
摘要： The present invention relates to a data processing configuration with a first circuit configuration (1) that connects a communication bus (2) with a second communication bus (3). The first circuit configuration (1) is the bus master of the first communication bus (2). Furthermore, a second circuit configuration (4) is connected with the first communication bus (2). By employing a wait signal (11), which is generated in the second circuit configuration (4) and transmitted to the first circuit configuration (1), it is possible to expand read and write access to the first communication bus (2) to any random number of clock cycles.
摘要翻译：本发明涉及一种具有连接通信总线（2）与第二通信总线（3）的第一电路配置（1）的数据处理配置。第一电路配置（1）是第一通信总线（2）的总线主机。此外，第二电路配置（4）与第一通信总线（2）连接。通过采用在第二电路配置（4）中产生并发送到第一电路配置（1）的等待信号（11），可以将对第一通信总线（2）的读取和写入访问扩展到任何随机数的时钟周期。

22. 发明授权

US06298407B1 Trigger points for performance optimization in bus-to-bus bridges 失效
标题翻译：总线到总线桥梁性能优化的触发点
公开(公告)号：US06298407B1
公开(公告)日：2001-10-02
申请号：US09034624
申请日：1998-03-04
申请人： Barry R. Davis , Nick G. Eskandari
发明人： Barry R. Davis , Nick G. Eskandari
IPC分类号： G06F1300
CPC分类号： G06F13/4054
摘要： Method and apparatus for tuning the performance of bridge devices, including PCI-to-PCI bridges as well as PCI local bus bridges (or host bridges). The embodiments of the invention permit a multiple-bus computer system to be tuned in view of the application and the bridge queue sizes. Such applications include those concerned with raw bandwidth (such as disk storage), and those that are sensitive to latency (such as networking and videoconferencing). The embodiments of the invention feature a control register that specifies storage conditions to be met by the read and write queues of the bridge. The programmed storage conditions are trigger points which cause the bridge to transfer data into or remove data from the queues during read and write transactions in order to promote the performance (throughput or latency) desired from the bridge.
摘要翻译：用于调整桥接器件性能的方法和装置，包括PCI到PCI桥以及PCI本地总线桥（或主机桥）。本发明的实施例允许根据应用和桥队列大小来调整多总线计算机系统。这些应用程序包括与原始带宽（如磁盘存储）有关的应用程序，以及对延迟敏感（如网络和视频会议）的应用程序。本发明的实施例的特征在于控制寄存器，其指定由桥的读取和写入队列要满足的存储条件。编程的存储条件是触发点，其导致桥接器在读取和写入事务期间将数据传送到队列中或从队列中移除数据，以便提升从桥接器所需的性能（吞吐量或等待时间）。

23. 发明授权

US06226703B1 Method and apparatus for reducing the apparent read latency when connecting busses with fixed read replay timeouts to CPU'S with write-back caches 有权
标题翻译：将具有固定读取重放超时的总线连接到具有回写缓存的CPU的总线时，可以减少表观读取延迟的方法和装置
公开(公告)号：US06226703B1
公开(公告)日：2001-05-01
申请号：US09188847
申请日：1998-11-09
申请人： Joseph Ervin , Jonathan Crowell
发明人： Joseph Ervin , Jonathan Crowell
IPC分类号： G06F1340
CPC分类号： G06F13/4054
摘要： An apparatus is provided for reducing read latency for an I/O device residing on a bus having a short read latency timeout period. The apparatus includes a I/O bridge on an I/O bus having a longer read latency timeout which modifies read transactions into two separate transactions, a write transaction to the same address requested by the read transaction which will force a write-back if the address hits in the CPU's write-back cache, and then performing the read transaction which is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the I/O bus having a short read latency timeout period from exceeding it's read latency timeout limit.
摘要翻译：提供了一种用于减少驻留在具有短读延迟超时周期的总线上的I / O设备的读延迟的装置。该装置包括I / O总线上的I / O桥，其具有较长的读取等待时间超时，该读取延迟超时将读取事务修改为两个单独的事务，对由读取事务请求的同一地址进行写入事务，这将强制回写，如果在CPU的写回缓存中的地址命中，然后执行在写入事务开始之后的预定时间段之后执行的读事务。这消除了I / O总线上的器件具有超过其读延迟超时限制的短读延迟超时周期的可能性。

24. 发明授权

US6075929A Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction 失效
标题翻译：预取数据以响应请求设备在等待事务中请求的数据时放弃对数据总线的控制的读取事务
公开(公告)号：US6075929A
公开(公告)日：2000-06-13
申请号：US658496
申请日：1996-06-05
申请人： John M. MacLaren
发明人： John M. MacLaren
IPC分类号： G06F13/36 , G06F12/02 , G06F12/08 , G06F13/40 , H01J13/00
CPC分类号： G06F13/4054 , G06F12/0215
摘要： A computer system includes a memory device on the first data bus, a requesting device that initiates a delayed memory read transaction on a second data bus, and a bridge device that delivers the delayed memory read transaction to the first data bus and receives from the first data bus completion data requested in the memory read transaction. The bridge device includes a data storage buffer that stores the completion data, and a buffer management element that automatically requests from the memory device additional data to be placed in the data storage buffer.
摘要翻译：计算机系统包括第一数据总线上的存储设备，在第二数据总线上启动延迟存储器读取事务的请求设备，以及将延迟的存储器读取事务传送到第一数据总线并从第一数据总线接收的桥接器件在存储器读取事务中请求的数据总线完成数据。桥接器件包括存储完成数据的数据存储缓冲器，以及缓冲器管理元件，其自动地从存储器件请求要放置在数据存储缓冲器中的附加数据。

25. 发明授权

US06021483A PCI-to-PCI bridges with a timer register for storing a delayed transaction latency 失效
标题翻译：具有定时器寄存器的PCI至PCI桥接器，用于存储延迟的事务延迟
公开(公告)号：US06021483A
公开(公告)日：2000-02-01
申请号：US40118
申请日：1998-03-17
申请人： Etai Adar , Ophir Nadir , Yehuda Peled
发明人： Etai Adar , Ophir Nadir , Yehuda Peled
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4054
摘要： To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface and an interface to a secondary subsystem for interconnecting a primary PCI bus system and the secondary subsystem. The system comprises a delayed transaction mechanism for enabling a transaction source attached to the primary PCI bus system to effect delayed transactions with a target in the secondary subsystem. This system has a programmable delay transaction timer which provides a degree of flexibility in the configuration of PCI systems. This flexibility can be exploited to provide considerable efficiency gains, albeit at the expense of some deviation of the strict requirements of the PCI Specification.
摘要翻译：为了提高包括至少一个与PCI总线的接口的总线到总线桥系统中的延迟交易的效率，公开了一种桥接系统，其包括至少一个主接口和到次级子系统的接口，用于将主PCI总线系统和辅助子系统。该系统包括用于使附接到主PCI总线系统的事务源能够实现次级子系统中的目标的延迟事务的延迟事务机制。该系统具有可编程延迟事务定时器，其在PCI系统的配置中提供了一定程度的灵活性。这种灵活性可以被利用来提供相当大的效率增益，尽管以PCI规范的严格要求有一些偏离为代价。

26. 发明授权

US5857082A Method and apparatus for quickly transferring data from a first bus to a second bus 失效
标题翻译：用于将数据从第一总线快速传送到第二总线的方法和装置
公开(公告)号：US5857082A
公开(公告)日：1999-01-05
申请号：US845801
申请日：1997-04-25
申请人： Robert N. Murdoch , Bruce A. Young , Tony M. Tarango , David J. Harriman
发明人： Robert N. Murdoch , Bruce A. Young , Tony M. Tarango , David J. Harriman
IPC分类号： G06F13/40
CPC分类号： G06F13/4054
摘要： A method and apparatus for transferring data from a first bus to a second bus. A bridge couples a first bus to a second bus. The bridge includes a buffer to store two data elements of a first packet transferred to the buffer from the first bus. The bridge also includes a controller that permits a first data element to be transferred from the buffer to the second bus. In addition, if at least a portion of a second packet has not been transferred to the bridge from the first bus, then the controller causes at least one wait state to be inserted on the second bus before transferring the second data element of the first packet from the buffer to the second bus.
摘要翻译：一种用于将数据从第一总线传送到第二总线的方法和装置。一座桥将第一班巴士连接到第二班车。该桥包括缓冲器，用于存储从第一总线传送到缓冲器的第一分组的两个数据元素。该桥还包括允许第一数据元件从缓冲器传送到第二总线的控制器。此外，如果第二分组的至少一部分尚未从第一总线传送到网桥，则在传送第一分组的第二数据元素之前，控制器使至少一个等待状态插入到第二总线上从缓冲区到第二条总线。

27. 发明授权

US5623694A Aborting an I/O operation started before all system data is received by the I/O controller after detecting a remote retry operation 失效
标题翻译：在检测到远程重试操作之后，I / O控制器接收到所有系统数据之前，中断I / O操作
公开(公告)号：US5623694A
公开(公告)日：1997-04-22
申请号：US316978
申请日：1994-10-03
申请人： Ravi K. Arimilli , John S. Dodson , Jerry D. Lewis
发明人： Ravi K. Arimilli , John S. Dodson , Jerry D. Lewis
IPC分类号： G06F13/00 , G06F11/14 , G06F13/40
CPC分类号： G06F13/4054 , G06F11/1407
摘要： A data processing system includes one or more processing units, a memory subsystem, and one or more input/output channel controllers, wherein each of the input/output channel controllers include the capability of speculative input/output execution. The speculative I/O execution technique according to the present invention may include several options. The speculative execution in the IOCC begins after receiving a raw address even though the operation can still be remotely retried. The programmed I/O latency time is reduced significantly due to the early speculative commencement of the IOCC operation. The IOCC may have to abort the speculative operation if a remote flow control retry is received. If, however, no retry is received then significant time is saved because the speculative operation proceeds.
摘要翻译：数据处理系统包括一个或多个处理单元，存储器子系统和一个或多个输入/输出通道控制器，其中每个输入/输出通道控制器包括投机输入/输出执行的能力。根据本发明的推测性I / O执行技术可以包括若干选项。即使该操作仍可远程重试，IOCC的投机执行在收到原始地址后开始。由于IOCC运营的早期投机开始，编程的I / O延迟时间显着降低。如果接收到远程流量控制重试，IOCC可能必须中止推测操作。然而，如果没有收到重试，那么由于投机操作进行而节省了大量时间。

28. 发明申请

US20160162426A1 OPTIMAL SAMPLING OF DATA-BUS SIGNALS USING CONFIGURABLE INDIVIDUAL TIME DELAYS 有权
标题翻译：使用可配置的个人时间延迟对数据总线信号进行最佳采样
公开(公告)号：US20160162426A1
公开(公告)日：2016-06-09
申请号：US14957617
申请日：2015-12-03
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Ofer Benjamin , Eldad Bar-Lev
IPC分类号： G06F13/362 , G06F13/40
CPC分类号： G06F13/3625 , G06F13/4031 , G06F13/4054
摘要： A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.
摘要翻译：一种方法包括在公共采样定时接收要采样的一组逻辑信号。针对组中的相应逻辑信号选择单独的时间延迟，其将每个逻辑信号单独地对准公共采样定时。每个逻辑信号被延迟相应的所选择的各个时间延迟，并且在公共采样定时对整个延迟的逻辑信号组进行采样。

29. 发明申请

US20160026603A1 BUS SYSTEM IN SOC 审中-公开
标题翻译：总线系统SOC
公开(公告)号：US20160026603A1
公开(公告)日：2016-01-28
申请号：US14873485
申请日：2015-10-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jaegeun YUN , Lingling LIAO , Bub-chul JEONG
IPC分类号： G06F13/42 , G06F13/28 , G06F13/40 , G06F13/364
CPC分类号： G06F13/4291 , G06F1/10 , G06F1/3237 , G06F13/28 , G06F13/364 , G06F13/405 , G06F13/4054 , G06F2213/0038 , Y02B70/12 , Y02B70/123 , Y02D10/128 , Y02D10/151
摘要： A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.
摘要翻译：一种片上系统总线系统，包括：总线，被配置为将片上系统的功能块彼此连接;以及时钟门控单元，连接到总线的接口单元，并且被配置为基本上对在根据事务检测信号的状态来操作安装在总线上的总线桥装置。

30. 发明申请

US20140372654A1 BRIDGE CIRCUITRY FOR COMMUNICATIONS WITH DYNAMICALLY RECONFIGURABLE CIRCUITS 有权
标题翻译：具有动态可重新连接电路的通信电路
公开(公告)号：US20140372654A1
公开(公告)日：2014-12-18
申请号：US13919899
申请日：2013-06-17
申请人： Altera Corporation
发明人： Robert L. Pelt , Sam Hedinger
IPC分类号： G06F13/38
CPC分类号： G06F13/4027 , G06F13/4018 , G06F13/404 , G06F13/4054
摘要： A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations during normal operation of the device. The bridge circuit may include interface circuitry coupled between first and second interfaces that communicate with the dynamically reconfigurable circuitry and the dedicated circuitry. Control circuitry may control the interface circuitry based on variable communications requirements of the second interface without interrupting communications with the dedicated circuitry at the first interface. The variable communications requirements may be dependent on which configuration of the dynamically reconfigurable circuitry is currently implemented.
摘要翻译：在设备的正常操作期间，可以使用桥接电路来在动态可重配置电路和具有静态配置的专用电路或其他电路之间进行接口。桥接电路可以包括耦合在与动态可重配置电路和专用电路通信的第一和第二接口之间的接口电路。控制电路可以基于第二接口的可变通信要求来控制接口电路，而不中断与第一接口处的专用电路的通信。可变通信要求可以取决于当前实现动态可重配置电路的哪个配置。

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