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1. 发明授权

US09864713B2 Optimal sampling of data-bus signals using configurable individual time delays 有权
公开(公告)号：US09864713B2
公开(公告)日：2018-01-09
申请号：US14957617
申请日：2015-12-03
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Ofer Benjamin , Eldad Bar-Lev
IPC分类号： G06F13/00 , H04L12/00 , G06F3/00 , G06F13/362 , G06F13/40
CPC分类号： G06F13/3625 , G06F13/4031 , G06F13/4054
摘要： A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.

2. 发明授权

US09385712B1 Impedance and duty cycle calibration in a driver circuit and a receiver circuit 有权
标题翻译：驱动电路和接收器电路中的阻抗和占空比校准
公开(公告)号：US09385712B1
公开(公告)日：2016-07-05
申请号：US14809877
申请日：2015-07-27
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Eldad Bar-Lev , Ofer Benjamin
IPC分类号： H03K19/00 , H03K19/0175 , H04L25/02
CPC分类号： H03K19/0005 , H04L25/0272 , H04L25/0278 , H04L25/028 , H04L25/0298
摘要： Some of the embodiments of the present disclosure provide a method including: communicating, by a first pin of an integrated circuit, with a device over a communication link, wherein the first pin is associated with a first impedance; selecting a plurality of impedance values for the first impedance; for ones of the plurality of impedance values, (i) transmitting a corresponding digital signal from the first pin over the communication link and (ii) generating a corresponding signal eye opening for the corresponding digital signal, such that a plurality of signal eye openings corresponding to a plurality of digitals signals for the corresponding plurality of impedance values are generated; comparing the plurality of signal eye openings; selecting a first impedance value of the plurality of impedance values; and transmitting signals over the communication link, with the first impedance being tuned to the first impedance value.
摘要翻译：本公开的一些实施例提供了一种方法，包括：通过集成电路的第一引脚与通信链路上的设备通信，其中第一引脚与第一阻抗相关联; 为所述第一阻抗选择多个阻抗值; 对于所述多个阻抗值中的一个，（i）通过所述通信链路从所述第一引脚发送相应的数字信号，以及（ii）为相应的数字信号产生相应的信号眼睛开度，使得对应于生成用于相应的多个阻抗值的多个数字信号; 比较多个信号眼孔; 选择所述多个阻抗值的第一阻抗值; 以及通过所述通信链路发射信号，其中所述第一阻抗被调谐到所述第一阻抗值。

3. 发明申请

US20160162426A1 OPTIMAL SAMPLING OF DATA-BUS SIGNALS USING CONFIGURABLE INDIVIDUAL TIME DELAYS 有权
标题翻译：使用可配置的个人时间延迟对数据总线信号进行最佳采样
公开(公告)号：US20160162426A1
公开(公告)日：2016-06-09
申请号：US14957617
申请日：2015-12-03
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Ofer Benjamin , Eldad Bar-Lev
IPC分类号： G06F13/362 , G06F13/40
CPC分类号： G06F13/3625 , G06F13/4031 , G06F13/4054
摘要： A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.
摘要翻译：一种方法包括在公共采样定时接收要采样的一组逻辑信号。针对组中的相应逻辑信号选择单独的时间延迟，其将每个逻辑信号单独地对准公共采样定时。每个逻辑信号被延迟相应的所选择的各个时间延迟，并且在公共采样定时对整个延迟的逻辑信号组进行采样。

4. 发明授权

US09094000B1 Impedance calibration in a driver circuit and a receiver circuit 有权
标题翻译：驱动电路和接收器电路中的阻抗校准
公开(公告)号：US09094000B1
公开(公告)日：2015-07-28
申请号：US13735722
申请日：2013-01-07
申请人： Marvell Israel (M.I.S.L.) Ltd.
发明人： Eldad Bar-Lev , Ofer Benjamin
IPC分类号： H03K17/16 , H03K19/003 , H03K5/12 , H04L25/02 , H03K19/00
CPC分类号： H03K19/0005 , H04L25/0272 , H04L25/0278 , H04L25/028 , H04L25/0298
摘要： Some of the embodiments of the present disclosure provide an integrated circuit communicating with a device over a multi-pin parallel bus, the integrated circuit comprising: at least a first pin and a second pin to communicate with the device over the multi-pin parallel bus; and an impedance tuning module disposed in the integrated circuit and configured to tune an impedance value of a first impedance associated the first pin separately from tuning an impedance value of a second impedance associated with the second pin.
摘要翻译：本公开的一些实施例提供了通过多引脚并行总线与器件通信的集成电路，该集成电路包括：至少第一引脚和第二引脚，用于通过多引脚并行总线与器件通信 ; 以及阻抗调谐模块，其布置在所述集成电路中并且被配置为与调节与所述第二引脚相关联的第二阻抗的阻抗值分别调整与所述第一引脚相关联的第一阻抗的阻抗值。

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