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1. 发明申请

US20050275372A1 Power controller for managing arrays of smart battery packs 审中-公开
标题翻译：用于管理智能电池组阵列的电源控制器
公开(公告)号：US20050275372A1
公开(公告)日：2005-12-15
申请号：US11151991
申请日：2005-06-14
申请人： Jonathan Crowell
发明人： Jonathan Crowell
IPC分类号： H02J7/00
CPC分类号： H02J7/0018 , H02J2007/0098
摘要： A power controller combines a multitude of smart battery packs into a single large bank, providing balanced charging and discharging. Battery packs are connected in parallel to form groups that may then be connected in series, while the specification limits for current and voltage of individual packs are maintained through microprocessor control of the battery pack charging circuits. The state of each pack is monitored, and charging of a pack at too high a charge is inhibited until the other packs in the group are sufficiently charged to allow balanced current-sharing. The state of each battery is broadcast on a bus to all processors so that each may determine whether there are enough packs of similar charge to safely source a load. The system preferably incorporates management firmware that allows user monitoring of the status of the power subsystem and all connected battery packs.
摘要翻译：电源控制器将大量智能电池组合成一个大型银行，提供均衡的充电和放电。电池组并联连接形成可以串联连接的组，而通过电池组充电电路的微处理器控制来维持单个组件的电流和电压的规格限制。监视每个包的状态，并且禁止以太高的电荷对包装进行充电，直到组中的其他包装被充分地充电以允许平衡的电流共享。每个电池的状态在总线上广播到所有处理器，使得每个电池可以确定是否有足够的类似电荷的包以安全地提供负载。该系统优选地包括管理固件，其允许用户监视电力子系统和所有连接的电池组的状态。

2. 发明授权

US5862358A Method and apparatus for reducing the apparent read latency when connecting busses with fixed read reply timeouts to CPUs with write-back caches 失效
标题翻译：将具有固定读取回复超时的总线连接到具有回写高速缓存的CPU时，可以减少表观读取延迟的方法和装置
公开(公告)号：US5862358A
公开(公告)日：1999-01-19
申请号：US856032
申请日：1997-05-14
申请人： Joseph Ervin , Jonathan Crowell
发明人： Joseph Ervin , Jonathan Crowell
IPC分类号： G06F13/40 , G06F13/14
CPC分类号： G06F13/4054
摘要： An apparatus is provided for reducing read latency for an I/O device residing on a first bus having a first, short read latency timeout period. The apparatus includes a I/O bridge on a second bus having a second, longer read latency timeout compared to that of first bus which modifies read transactions into two separate transactions. A first transaction is a write transaction to the same address requested by the read transaction. This transaction forces a write-back if the address hits in a CPU's write-back cache. Thereafter the read transaction is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the first bus having a short read latency timeout period from exceeding it's read latency timeout limit.
摘要翻译：提供了一种用于减少驻留在具有第一短读延迟超时周期的第一总线上的I / O设备的读延迟的装置。该装置包括在第二总线上的I / O桥，其具有与将第一总线相比较的更长的读延迟超时，其将读取事务修改为两个单独的事务。第一个事务是对读取事务请求的同一地址的写入事务。如果地址在CPU的回写缓存中，该事务强制回写。此后，在写入事务开始之后的预定时间段之后执行读取事务。这消除了在第一总线上的设备具有超过其读延迟超时限制的短读延迟超时周期的可能性。

3. 发明申请

US20080037370A1 UNDERWATER ACOUSTIC POSITIONING SYSTEM AND METHOD 有权
标题翻译：水下定位系统及方法
公开(公告)号：US20080037370A1
公开(公告)日：2008-02-14
申请号：US11464579
申请日：2006-08-15
申请人： Jonathan Crowell
发明人： Jonathan Crowell
IPC分类号： G01S3/80
CPC分类号： G01S5/30 , H04B11/00
摘要： A method for determining the position of an underwater device includes placement of a plurality of station keeping devices on or below the surface of the water in known positions. A device to locate is provided for placement below the surface of the water, and the device to locate and the station keeping devices are provided with a synchronized time base and a common acoustic pulse time schedule. Each station keeping device sends an acoustic pulse at a time according to the common acoustic pulse schedule. The device to locate receives pulses sent by the station keeping devices and calculates a distance between itself and each station keeping device based upon the time that the acoustic pulse is sent and the time that the pulse is received. The device to locate then calculates its position based upon the distances between the device to locate and the station keeping devices. Systems and devices are also disclosed.
摘要翻译：一种用于确定水下装置的位置的方法包括在已知位置的水表面上或下方放置多个站保持装置。提供用于定位的设备用于放置在水面以下，并且定位设备和站保持设备具有同步的时基和公共声脉冲时间表。每个站保持装置根据公共声脉冲时间表一次发送声脉冲。定位装置接收由站保持装置发送的脉冲，并且基于发送声脉冲的时间和接收脉冲的时间来计算其与每个站保持装置之间的距离。然后，定位的设备将根据要定位的设备与驻车设备之间的距离来计算其位置。还公开了系统和装置。

4. 发明授权

US06226703B1 Method and apparatus for reducing the apparent read latency when connecting busses with fixed read replay timeouts to CPU'S with write-back caches 有权
标题翻译：将具有固定读取重放超时的总线连接到具有回写缓存的CPU的总线时，可以减少表观读取延迟的方法和装置
公开(公告)号：US06226703B1
公开(公告)日：2001-05-01
申请号：US09188847
申请日：1998-11-09
申请人： Joseph Ervin , Jonathan Crowell
发明人： Joseph Ervin , Jonathan Crowell
IPC分类号： G06F1340
CPC分类号： G06F13/4054
摘要： An apparatus is provided for reducing read latency for an I/O device residing on a bus having a short read latency timeout period. The apparatus includes a I/O bridge on an I/O bus having a longer read latency timeout which modifies read transactions into two separate transactions, a write transaction to the same address requested by the read transaction which will force a write-back if the address hits in the CPU's write-back cache, and then performing the read transaction which is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the I/O bus having a short read latency timeout period from exceeding it's read latency timeout limit.
摘要翻译：提供了一种用于减少驻留在具有短读延迟超时周期的总线上的I / O设备的读延迟的装置。该装置包括I / O总线上的I / O桥，其具有较长的读取等待时间超时，该读取延迟超时将读取事务修改为两个单独的事务，对由读取事务请求的同一地址进行写入事务，这将强制回写，如果在CPU的写回缓存中的地址命中，然后执行在写入事务开始之后的预定时间段之后执行的读事务。这消除了I / O总线上的器件具有超过其读延迟超时限制的短读延迟超时周期的可能性。

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