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21. 发明授权

US09553566B2 Hybrid driver circuit 有权
标题翻译：混合驱动电路
公开(公告)号：US09553566B2
公开(公告)日：2017-01-24
申请号：US14564618
申请日：2014-12-09
申请人： MoSys, Inc.
发明人： Eric D. Groen , Charles W. Boecker
IPC分类号： H03K3/012 , H03K19/00 , H03K19/003 , H03K17/687
CPC分类号： H03K3/012 , G05F1/577 , G05F1/59 , H03K17/687 , H03K19/0016 , H03K19/00361 , H03K19/00369
摘要： In one embodiment, a voltage mode driver circuit includes a first voltage adjusting circuit configured to provide an adjustable first pseudo-supply voltage to a first node based on a first supply voltage, including generating the first pseudo-supply voltage based on a first reference voltage and feedback from the first node. In this embodiment, the voltage mode driver circuit includes switching circuitry configured to selectively couple one of the first node or a second node to a first differential output terminal and a different one of the first node or the second node to a second differential output terminal based on a data signal. In this embodiment, the voltage mode driver circuit includes a current mode emphasis driver configured to selectively couple one of the first differential output terminal or the second differential output terminal to a first set of one or more current supplies and a different one of the first differential output terminal or second differential output terminal to a second set of one or more current supplies, based on one or more emphasis signals.
摘要翻译：在一个实施例中，电压模式驱动器电路包括第一电压调整电路，其被配置为基于第一电源电压向第一节点提供可调节的第一伪电源电压，包括基于第一参考电压产生第一伪电源电压和来自第一个节点的反馈。在该实施例中，电压模式驱动器电路包括被配置为选择性地将第一节点或第二节点之一耦合到第一差分输出端和第一节点或第二节点中的不同一个到第二差分输出终端的开关电路在数据信号上。在该实施例中，电压模式驱动器电路包括电流模式强调驱动器，其被配置为选择性地将第一差分输出端或第二差分输出端中的一个耦合到第一组一个或多个电流源和第一差分输出端子或第二差分输出端子连接到基于一个或多个强调信号的一个或多个电流源的第二组。

22. 发明授权

US09342471B2 High utilization multi-partitioned serial memory 有权
标题翻译：高利用率多分区串行存储器
公开(公告)号：US09342471B2
公开(公告)日：2016-05-17
申请号：US12697141
申请日：2010-01-29
申请人： Michael J. Miller , Richard S. Roy
发明人： Michael J. Miller , Richard S. Roy
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1647
摘要： A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.
摘要翻译：一种存储装置，包括在第一多个串行链路上接收指令和输入数据的输入接口。指令和输入数据在存储器件上反序列化，并被提供给存储器控制器。存储器控制器响应于接收的指令启动对存储器内核的访问。存储器核心包括以循环和重叠的方式访问的多个存储器分区。这允许每个存储器分区以比串行链路更低的频率工作，同时正确地维护接收到的指令。以同步方式执行对存储设备的访问，其中每个访问呈现已知的固定等待时间。

23. 发明申请

US20160019029A1 Method and Apparatus for Randomizer 有权
标题翻译：随机机的方法和装置
公开(公告)号：US20160019029A1
公开(公告)日：2016-01-21
申请号：US14839576
申请日：2015-08-28
申请人： MoSys, Inc.
发明人： Michael J. MILLER , Michael J. MORRISON , Jay B. PATEL
IPC分类号： G06F7/58
CPC分类号： G06F7/582
摘要： A Method and Apparatus for Randomizer has been disclosed. In one implementation a sequence of randomized connections then exclusive-OR operations and then an adder produce a randomized output.
摘要翻译：已经公开了一种随机器的方法和装置。在一个实现中，随机连接序列然后是异或运算，然后是加法器产生随机输出。

24. 发明授权

US08704570B2 Delay-locked loop with phase adjustment 有权
标题翻译：延时锁相环调相
公开(公告)号：US08704570B2
公开(公告)日：2014-04-22
申请号：US13720981
申请日：2012-12-19
申请人： Aldo Bottelli , Prashant Choudhary , Charles W Boecker
发明人： Aldo Bottelli , Prashant Choudhary , Charles W Boecker
IPC分类号： H03L7/06
CPC分类号： H03L1/00 , H03L7/07 , H03L7/08 , H03L7/0816 , H04L7/0338
摘要： A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
摘要翻译：延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

25. 发明授权

US08460995B2 Method of forming a MIM capacitor 有权
标题翻译：形成MIM电容器的方法
公开(公告)号：US08460995B2
公开(公告)日：2013-06-11
申请号：US12804855
申请日：2010-07-30
申请人： Jeong Y. Choi
发明人： Jeong Y. Choi
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10855 , H01L27/10882 , H01L27/10888
摘要： An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the memory region than in the logic region.
摘要翻译：嵌入式存储器系统包括与逻辑晶体管阵列相同的衬底上的随机存取存储器（RAM）单元阵列。每个RAM单元包括存取晶体管和电容器结构。通过在电介质层中形成金属 - 绝缘体 - 金属电容器来制造电容器结构。嵌入式RAM系统在存储器区域中比在逻辑区域中包括更少的金属层。

26. 发明授权

US08451675B2 Methods for accessing DRAM cells using separate bit line control 有权
标题翻译：使用单独的位线控制访问DRAM单元的方法
公开(公告)号：US08451675B2
公开(公告)日：2013-05-28
申请号：US13077811
申请日：2011-03-31
申请人： Richard S. Roy , Dipak K. Sikdar
发明人： Richard S. Roy , Dipak K. Sikdar
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C11/4097 , G11C2207/005
摘要： A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.
摘要翻译：存储器系统，其包括耦合到第一组动态随机存取存储器（DRAM）单元的第一位线，耦合到第二组DRAM单元的第二（互补）位线以及耦合到第一和第二位线。感测放大器包括耦合在第一和第二位线之间的一对交叉耦合的反相器（或类似的锁存电路）以及将第一位线耦合到第一全局位线的第一选择晶体管和第二选择晶体管将第二位线耦合到第二全局位线。第一和第二选择晶体管被独立地控制，从而能够实现改进的读和写访问序列，从而消除与位线耦合相关联的信号丢失，消除“读取凸起”条件，并消除后期写入条件。

27. 发明授权

US08436660B2 Voltage-mode driver with equalization 有权
标题翻译：电压模式驱动器均衡
公开(公告)号：US08436660B2
公开(公告)日：2013-05-07
申请号：US12870549
申请日：2010-08-27
申请人： Charles W. Boecker
发明人： Charles W. Boecker
IPC分类号： H03K3/00
CPC分类号： H03K19/00361 , H03K19/017 , H03K19/0948 , H04L25/0272 , Y10T307/50
摘要： A voltage-mode differential driver may include a first nominal path that selectively couples a first supply or a second supply to a first output terminal in response to an input data. The voltage-mode differential driver may further include a first capacitive boost path that selectively couples the first supply or the second supply to the first output terminal responsive to the input data. The first capacitive boost path may be selectively enabled to provide a boost current to be added to a current from the first nominal path resulting in an output current to be provided to the first output terminal.
摘要翻译：电压模式差分驱动器可以包括响应于输入数据选择性地将第一电源或第二电源耦合到第一输出端的第一标称路径。电压模式差分驱动器还可以包括响应于输入数据选择性地将第一电源或第二电源耦合到第一输出端的第一电容升压路径。可以选择性地使第一电容性升压路径提供要被加到来自第一标称路径的电流的升压电流，从而产生要提供给第一输出端的输出电流。

28. 发明申请

US20120250442A1 Methods For Accessing DRAM Cells Using Separate Bit Line Control 有权
标题翻译：使用单独的位线控制访问DRAM单元的方法
公开(公告)号：US20120250442A1
公开(公告)日：2012-10-04
申请号：US13077811
申请日：2011-03-31
申请人： Richard S. Roy , Dipak K. Sikdar
发明人： Richard S. Roy , Dipak K. Sikdar
IPC分类号： G11C7/12
CPC分类号： G11C11/4091 , G11C11/4097 , G11C2207/005
摘要： A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.
摘要翻译：存储器系统，其包括耦合到第一组动态随机存取存储器（DRAM）单元的第一位线，耦合到第二组DRAM单元的第二（互补）位线以及耦合到第一和第二位线。感测放大器包括耦合在第一和第二位线之间的一对交叉耦合的反相器（或类似的锁存电路）以及将第一位线耦合到第一全局位线的第一选择晶体管和第二选择晶体管将第二位线耦合到第二全局位线。独立地控制第一和第二选择晶体管，由此能够实现改进的读和写访问序列，从而消除与位线耦合相关联的信号损耗，消除读取凸起条件，并消除后期写入条件。

29. 发明授权

US08274326B2 Equalization circuit 有权
标题翻译：均衡电路
公开(公告)号：US08274326B2
公开(公告)日：2012-09-25
申请号：US12872852
申请日：2010-08-31
申请人： Charles W. Boecker
发明人： Charles W. Boecker
IPC分类号： H03F1/14 , H03F1/34 , H03F3/18 , H04B7/005
CPC分类号： H03F1/301 , H03F3/45179 , H03F3/45632 , H03F2203/45082 , H03F2203/45544 , H03F2203/45594 , H04L25/03885 , H04L2025/0349
摘要： An equalization circuit includes a first differential amplifier having first and second transistors, and a first differential high-pass filter coupled to respective gate terminals of the first and second transistors. A source terminal of the first transistor is coupled to a first input node, and a source terminal of the second transistor is coupled to the second input node. The equalization circuit further includes a second differential amplifier having third and fourth transistors, and a second differential high-pass filter coupled to respective gate terminals of each of the third and fourth transistors. A source terminal of the third transistor is coupled to the first input node, and a source terminal of the second transistor is coupled to the second input node. Using such a circuit, continuous time decision feedback equalization may be performed.
摘要翻译：均衡电路包括具有第一和第二晶体管的第一差分放大器和耦合到第一和第二晶体管的相应栅极端的第一差分高通滤波器。第一晶体管的源极端子耦合到第一输入节点，并且第二晶体管的源极端子耦合到第二输入节点。均衡电路还包括具有第三和第四晶体管的第二差分放大器和耦合到第三和第四晶体管中的每一个的相应栅极端的第二差分高通滤波器。第三晶体管的源极端子耦合到第一输入节点，并且第二晶体管的源极端子耦合到第二输入节点。使用这样的电路，可以执行连续时间判定反馈均衡。

30. 发明申请

US20120054704A1 VOLTAGE-MODE DRIVER WITH EQUALIZATION 有权
标题翻译：具有均衡的电压模式驱动器
公开(公告)号：US20120054704A1
公开(公告)日：2012-03-01
申请号：US12870549
申请日：2010-08-27
申请人： Charles Walter Boecker
发明人： Charles Walter Boecker
IPC分类号： G06F17/50 , H02J4/00
CPC分类号： H03K19/00361 , H03K19/017 , H03K19/0948 , H04L25/0272 , Y10T307/50
摘要： A voltage-mode differential driver may include a first nominal path that selectively couples a first supply or a second supply to a first output terminal in response to an input data. The voltage-mode differential driver may further include a first capacitive boost path that selectively couples the first supply or the second supply to the first output terminal responsive to the input data. The first capacitive boost path may be selectively enabled to provide a boost current to be added to a current from the first nominal path resulting in an output current to be provided to the first output terminal.
摘要翻译：电压模式差分驱动器可以包括响应于输入数据选择性地将第一电源或第二电源耦合到第一输出端的第一标称路径。电压模式差分驱动器还可以包括响应于输入数据选择性地将第一电源或第二电源耦合到第一输出端的第一电容升压路径。可以选择性地使第一电容性升压路径提供要被加到来自第一标称路径的电流的升压电流，从而产生要提供给第一输出端的输出电流。

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