专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08704570B2 Delay-locked loop with phase adjustment 有权
标题翻译：延时锁相环调相
公开(公告)号：US08704570B2
公开(公告)日：2014-04-22
申请号：US13720981
申请日：2012-12-19
申请人： Aldo Bottelli , Prashant Choudhary , Charles W Boecker
发明人： Aldo Bottelli , Prashant Choudhary , Charles W Boecker
IPC分类号： H03L7/06
CPC分类号： H03L1/00 , H03L7/07 , H03L7/08 , H03L7/0816 , H04L7/0338
摘要： A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
摘要翻译：延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

2. 发明申请

US20130154698A1 DELAY-LOCKED LOOP WITH PHASE ADJUSTMENT 有权
标题翻译：延迟锁定环路进行相位调整
公开(公告)号：US20130154698A1
公开(公告)日：2013-06-20
申请号：US13720981
申请日：2012-12-19
申请人： Aldo Bottelli , Prashant Choudhary , Charles W. Boecker
发明人： Aldo Bottelli , Prashant Choudhary , Charles W. Boecker
IPC分类号： H03L7/07
CPC分类号： H03L1/00 , H03L7/07 , H03L7/08 , H03L7/0816 , H04L7/0338
摘要： A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
摘要翻译：延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

3. 发明授权

US07394849B2 Decision feedback equalizer with dynamic feedback control 有权
标题翻译：具有动态反馈控制的决策反馈均衡器
公开(公告)号：US07394849B2
公开(公告)日：2008-07-01
申请号：US11539810
申请日：2006-10-09
申请人： Edem Ibragimov , Qian Yu , Prashant Choudhary
发明人： Edem Ibragimov , Qian Yu , Prashant Choudhary
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H03H21/0012 , H03H2021/0096 , H04L25/03063 , H04L25/0307 , H04L2025/0349 , H04L2025/03509 , H04L2025/03611
摘要： A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is controlled by a signal formed as a combination of feedback and feedforward signals. The feedback signal is an error signal related to a difference between pre-slicer and post-slicer signals. The feedforward signal is formed by differentiating and delaying the incoming data signal.
摘要翻译：具有用于自适应信号均衡器的动态反馈控制的判决反馈均衡器。动态控制决策反馈环路内的定时，以优化输出信号限幅器对数据信号的恢复。动态定时由形成为反馈和前馈信号的组合的信号控制。反馈信号是与预切片器和后切片器信号之间的差异相关的误差信号。前馈信号通过差分和延迟输入数据信号来形成。

4. 发明申请

US20110258591A1 METHOD AND APPARATUS TO OPTIMIZE ADAPTIVE RADIO-FREQUENCY SYSTEMS 有权
标题翻译：优化自适应无线电频率系统的方法和装置
公开(公告)号：US20110258591A1
公开(公告)日：2011-10-20
申请号：US12762098
申请日：2010-04-16
申请人： Arvind V. Keerthi , Prashant Choudhary
发明人： Arvind V. Keerthi , Prashant Choudhary
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/08 , G06F2217/78
摘要： A performance optimizing circuit is provided for a signal processing system which is parameterized by a set of coefficients that vary the operational characteristics of the signal processing system. The performance optimizing circuit receives as input a reference signal and an output signal of the signal processing system. The performance optimizing circuit may include (a) a cost computation circuit that receives the reference signal and the output signal and provides as output a cost signal representing a cost function computed using a set of current values for the set of coefficients, the output signal and the reference signal; and (b) a cost optimizer circuit that, at each of a plurality of successive time intervals, evaluates one or more values of the cost signal in the cost computation circuit and provides to the signal processing system a new set of values for the set of coefficients. The cost optimizer circuit implements two or more of the random search, parabolic interpolation and hill climbing techniques.
摘要翻译：为信号处理系统提供性能优化电路，该信号处理系统由改变信号处理系统的操作特性的一组系数参数化。性能优化电路接收信号处理系统的参考信号和输出信号作为输入。性能优化电路可以包括（a）成本计算电路，其接收参考信号和输出信号，并提供代表使用一组系数的当前值所计算的成本函数的成本信号作为输出，输出信号和参考信号; 以及（b）成本优化器电路，其在多个连续时间间隔中的每一个处评估所述成本计算电路中的所述成本信号的一个或多个值，并向所述信号处理系统提供所述一组系数。成本优化器电路实现了随机搜索，抛物线插值和爬山技术中的两种或多种。

5. 发明授权

US07120193B2 Decision feedback equalizer with dynamic feedback control 有权
标题翻译：具有动态反馈控制的决策反馈均衡器
公开(公告)号：US07120193B2
公开(公告)日：2006-10-10
申请号：US11070485
申请日：2005-03-02
申请人： Edem Ibragimov , Qian Yu , Prashant Choudhary
发明人： Edem Ibragimov , Qian Yu , Prashant Choudhary
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H03H21/0012 , H03H2021/0096 , H04L25/03063 , H04L25/0307 , H04L2025/0349 , H04L2025/03509 , H04L2025/03611
摘要： A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer.
摘要翻译：具有用于自适应信号均衡器的动态反馈控制的判决反馈均衡器。动态控制决策反馈环路内的定时，以优化输出信号限幅器对数据信号的恢复。

6. 发明申请

US20050104158A1 COMPACT, HIGH Q INDUCTOR FOR INTEGRATED CIRCUIT 审中-公开
标题翻译： COMPACT，用于集成电路的高Q电感器
公开(公告)号：US20050104158A1
公开(公告)日：2005-05-19
申请号：US10718501
申请日：2003-11-19
申请人： Jishnu Bhattacharjee , Madabusi Govindarajan , Debanjan Mukherjee , Abhijit Phanse , Prashant Choudhary
发明人： Jishnu Bhattacharjee , Madabusi Govindarajan , Debanjan Mukherjee , Abhijit Phanse , Prashant Choudhary
IPC分类号： H01L21/02 , H01L23/522 , H01L29/00
CPC分类号： H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An inductor for an integrated circuit made of a plurality of stacked, electrically coupled, metal layers. Each metal layer includes an inductor formed of a spiral pattern, which except for the top and bottom inductors, are electrically coupled to the spiral inductor formed on the metal layer above and below with an electrical path or via formed between each metal layer. The top and bottom inductors are electrically coupled to the inductor directly below and above, respectively.
摘要翻译：一种用于由多个堆叠的电耦合的金属层制成的集成电路的电感器。每个金属层包括由螺旋图案形成的电感器，除了顶部和底部电感器之外，通过在每个金属层之间形成的电路径或通孔电连接到形成在金属层上的螺旋电感器上方和下方。顶部和底部电感器分别电连接到电感器上方。

7. 发明授权

US06516027B1 Method and apparatus for discrete multitone communication bit allocation 有权
标题翻译：用于离散多音通信位分配的方法和装置
公开(公告)号：US06516027B1
公开(公告)日：2003-02-04
申请号：US09252418
申请日：1999-02-18
申请人： Samir Kapoor , Prashant Choudhary
发明人： Samir Kapoor , Prashant Choudhary
IPC分类号： H04B346
CPC分类号： H04L5/006 , H04L5/0007 , H04L5/0046 , H04L5/1438
摘要： A method and apparatus for allocating bits to subchannels in a discrete multitone environment. The method employs the use of precalculated and prestored look-up tables which take into account a desired bit error rate, signal-to-noise ratio gap for a particular coding scheme, and gain scaling factor. This eliminates the need for the communication device to conduct complex and time consuming calculations. During the training sequence portion of data communication channel establishment, the measured signal-to-noise ratio for each subchannel is compared with values in the precalculated look-up tables to determine the bit allocation for that subchannel. The bit allocation value is stored in a data structure in the communication device. A gain scaling factor for each subchannel is then determined and stored as a data structure. The bit allocation and gain scaling data can then be transmitted to a partner communication device in order to instruct the transmitter how to load each subchannel.
摘要翻译：一种用于在离散多媒体环境中分配比特到子信道的方法和装置。该方法采用预先计算和预存的查找表，其考虑了特定编码方案的期望误码率，信噪比间隙以及增益缩放因子。这消除了对通信设备进行复杂和耗时的计算的需要。在数据通信信道建立的训练序列部分期间，将每个子信道的测量信噪比与预先计算的查找表中的值进行比较，以确定该子信道的比特分配。位分配值存储在通信设备中的数据结构中。然后确定每个子信道的增益比例因子并将其存储为数据结构。然后可以将比特分配和增益缩放数据发送到伙伴通信设备，以便指示发射机如何加载每个子信道。

8. 发明授权

US11311135B2 Image processing by determining combined image distances using dual path analyses 有权
公开(公告)号：US11311135B2
公开(公告)日：2022-04-26
申请号：US16671514
申请日：2019-11-01
申请人： Prashant Choudhary
发明人： Prashant Choudhary
IPC分类号： A47J27/00 , A23L5/10 , A47J36/32 , G06N20/00
摘要： Image analysis for comparison utilizes a combined image distance determined between the one or more captured images and the one or more reference images from a dual path analysis. The dual path analysis can comprise a first image analysis based on histograms of image colors and a second image analysis based a one-dimensional power spectral density of a black and white instance of the one or more captured images and the one or more reference images. In one case, the one-dimensional power spectral density derived by integrating a Discrete Fourier Transform of a two-dimensional image over annular rings of substantially equal area starting from the center of the two-dimensional image.

9. 发明授权

US08136081B2 Method and apparatus to optimize adaptive radio-frequency systems 有权
标题翻译：优化自适应射频系统的方法和装置
公开(公告)号：US08136081B2
公开(公告)日：2012-03-13
申请号：US12762098
申请日：2010-04-16
申请人： Arvind V. Keerthi , Prashant Choudhary
发明人： Arvind V. Keerthi , Prashant Choudhary
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/08 , G06F2217/78
摘要： A performance optimizing circuit is provided for a signal processing system which is parameterized by a set of coefficients that vary the operational characteristics of the signal processing system. The performance optimizing circuit receives as input a reference signal and an output signal of the signal processing system. The performance optimizing circuit may include (a) a cost computation circuit that receives the reference signal and the output signal and provides as output a cost signal representing a cost function computed using a set of current values for the set of coefficients, the output signal and the reference signal; and (b) a cost optimizer circuit that, at each of a plurality of successive time intervals, evaluates one or more values of the cost signal in the cost computation circuit and provides to the signal processing system a new set of values for the set of coefficients. The cost optimizer circuit implements two or more of the random search, parabolic interpolation and hill climbing techniques.
摘要翻译：为信号处理系统提供性能优化电路，该信号处理系统由改变信号处理系统的操作特性的一组系数参数化。性能优化电路接收信号处理系统的参考信号和输出信号作为输入。性能优化电路可以包括（a）成本计算电路，其接收参考信号和输出信号，并提供代表使用一组系数的当前值所计算的成本函数的成本信号作为输出，输出信号和参考信号; 以及（b）成本优化器电路，其在多个连续时间间隔中的每一个处评估所述成本计算电路中的所述成本信号的一个或多个值，并向所述信号处理系统提供所述一组系数。成本优化器电路实现了随机搜索，抛物线插值和爬山技术中的两种或多种。

10. 发明授权

US07421022B2 Method for robust and stable convergence of blind LMS based adaptation of coefficients for a continuous time FFE-DFE 有权
标题翻译：用于连续时间FFE-DFE的基于LMS的盲系数适应系数的稳健和稳定收敛的方法
公开(公告)号：US07421022B2
公开(公告)日：2008-09-02
申请号：US11115506
申请日：2005-04-27
申请人： Prashant Choudhary , Venugopal Balasubramonian , Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse , Abhijit Shanbhag , Qian Yu
发明人： Prashant Choudhary , Venugopal Balasubramonian , Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse , Abhijit Shanbhag , Qian Yu
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/0307 , H04L2025/03598
摘要： A continuous time electronic dispersion compensation architecture using feed forward equalization and a non-linear decision feedback equalization forms an output signal by a linear combination of successively delayed versions of the input signal and the sliced output signal weighted by appropriate coefficients. A selected number of taps in the mixer used to generate a corresponding number of coefficients for use in the feed forward equalizer are held to a selected voltage to ensure that the coefficients associated with these two taps do not drift. This causes the other coefficients to converge to a unique minimum square error value. In one embodiment the selected voltage is the maximum system voltage.
摘要翻译：使用前馈均衡和非线性判决反馈均衡的连续时间电子色散补偿架构通过输入信号的连续延迟版本和由适当系数加权的分片输出信号的线性组合形成输出信号。用于产生用于前馈均衡器的相应数量的系数的混频器中的选定数量的抽头被保持到所选择的电压，以确保与这两个抽头相关联的系数不漂移。这导致其他系数收敛到唯一的最小平方误差值。在一个实施例中，所选择的电压是最大系统电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式