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1. 发明授权

US06690202B1 Correction of duty-cycle distortion in communications and other circuits 有权
标题翻译：通信和其他电路中占空比失真的校正
公开(公告)号：US06690202B1
公开(公告)日：2004-02-10
申请号：US10294254
申请日：2002-11-13
申请人： Eric Douglas Groen , Charles Walter Boecker
发明人： Eric Douglas Groen , Charles Walter Boecker
IPC分类号： H03K508
CPC分类号： H03K5/007 , H03K5/082 , H03K5/1565
摘要： In some communications circuits a phenomenon called duty-cycle distortion—that is, a distortion of the apparent duration of the pulses in clock signals—causes the circuits to read clock signals as having a different duration than intended. Accordingly, the inventors devised unique circuitry for correcting or preventing this distortion. One exemplary circuit uses a voltage divider, comprising a pair of transistors, to set the DC or average voltage of the clock signals input to the digital circuit at a level approximating the logic threshold voltage of the digital circuit. In another example, a feedback circuit drives the DC or average voltage of signals input to the digital circuit to match a reference voltage that is substantially equal to the logic threshold voltage. In both examples, equating the DC or average voltage of the clock signals to the logic threshold voltage of the digital circuit reduces or prevents duty-cycle distortion.
摘要翻译：在一些通信电路中，称为占空比失真的现象（即，时钟信号中的脉冲的视在持续时间的失真）导致电路将时钟信号读取为具有与预期不同的持续时间。因此，发明人设计了用于校正或防止这种失真的独特电路。一个示例性电路使用包括一对晶体管的分压器来将输入到数字电路的时钟信号的DC或平均电压设置在接近数字电路的逻辑阈值电压的电平。在另一示例中，反馈电路驱动输入到数字电路的信号的DC或平均电压以匹配基本上等于逻辑阈值电压的参考电压。在这两个例子中，将时钟信号的直流或平均电压等同于数字电路的逻辑门限电压，可以降低或防止占空比失真。

2. 发明授权

US06507220B1 Correction of duty-cycle distortion in communications and other circuits 有权
标题翻译：通信和其他电路中占空比失真的校正
公开(公告)号：US06507220B1
公开(公告)日：2003-01-14
申请号：US09968471
申请日：2001-09-28
申请人： Eric Douglas Groen , Charles Walter Boecker
发明人： Eric Douglas Groen , Charles Walter Boecker
IPC分类号： H03K1900
CPC分类号： H03K5/007 , H03K5/082 , H03K5/1565
摘要： A typical occurrence in communication circuits, such as transmitters and receivers, is the internal transfer of a sequence of pulses, known as a clock signal, from an amplifier to a digital circuit. For proper operation, it is critical that the digital circuit accurately comprehends the clock signal. However, in some communications circuits a phenomenon called duty-cycle distortion—that is, a distortion of the apparent duration of the pulses in clock signals—causes the digital circuit to read the clock signals as having a longer or shorter duration than intended. Accordingly, the inventors devised unique circuitry for correcting or preventing this distortion. One exemplary circuit uses a voltage divider, comprising a pair of transistors, to set the DC or average voltage of the clock signals input to the digital circuit at a level approximating the logic threshold voltage of the digital circuit. In another example, a feedback circuit drives the DC or average voltage of signals input to the digital circuit to match a reference voltage that is substantially equal to the logic threshold voltage. In both examples, equating the DC or average voltage of the clock signals to the logic threshold voltage of the digital circuit reduces or prevents duty-cycle distortion.
摘要翻译：诸如发射机和接收机之类的通信电路中的典型发生是从放大器到数字电路的脉冲序列（称为时钟信号）的内部传送。为了正确的操作，数字电路必须准确地理解时钟信号。然而，在一些通信电路中，称为占空比失真的现象（即时钟信号中的脉冲的视在持续时间的失真）导致数字电路将时钟信号读取为具有比预期更长或更短的持续时间。因此，发明人设计了用于校正或防止这种失真的独特电路。一个示例性电路使用包括一对晶体管的分压器来将输入到数字电路的时钟信号的DC或平均电压设置在接近数字电路的逻辑阈值电压的电平。在另一示例中，反馈电路驱动输入到数字电路的信号的DC或平均电压以匹配基本上等于逻辑阈值电压的参考电压。在这两个例子中，将时钟信号的直流或平均电压等同于数字电路的逻辑门限电压，可以降低或防止占空比失真。

3. 发明申请

US20120054704A1 VOLTAGE-MODE DRIVER WITH EQUALIZATION 有权
标题翻译：具有均衡的电压模式驱动器
公开(公告)号：US20120054704A1
公开(公告)日：2012-03-01
申请号：US12870549
申请日：2010-08-27
申请人： Charles Walter Boecker
发明人： Charles Walter Boecker
IPC分类号： G06F17/50 , H02J4/00
CPC分类号： H03K19/00361 , H03K19/017 , H03K19/0948 , H04L25/0272 , Y10T307/50
摘要： A voltage-mode differential driver may include a first nominal path that selectively couples a first supply or a second supply to a first output terminal in response to an input data. The voltage-mode differential driver may further include a first capacitive boost path that selectively couples the first supply or the second supply to the first output terminal responsive to the input data. The first capacitive boost path may be selectively enabled to provide a boost current to be added to a current from the first nominal path resulting in an output current to be provided to the first output terminal.
摘要翻译：电压模式差分驱动器可以包括响应于输入数据选择性地将第一电源或第二电源耦合到第一输出端的第一标称路径。电压模式差分驱动器还可以包括响应于输入数据选择性地将第一电源或第二电源耦合到第一输出端的第一电容升压路径。可以选择性地使第一电容性升压路径提供要被加到来自第一标称路径的电流的升压电流，从而产生要提供给第一输出端的输出电流。

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