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21. 发明授权

US5862184A Mapper for high data rate transmission through channels subject to robbed bit signalling 失效
标题翻译：映射器，用于通过抢占位信令的信道进行高数据速率传输
公开(公告)号：US5862184A
公开(公告)日：1999-01-19
申请号：US838367
申请日：1997-04-08
申请人： Yuri Goldstein , Yuri Okunev
发明人： Yuri Goldstein , Yuri Okunev
IPC分类号： H03M7/00 , H04B14/02 , H04B14/04 , H04L25/49 , H04L27/00 , H04L27/02 , H04L27/34 , H04L27/04
CPC分类号： H04B14/023 , H04B14/048 , H04L25/4927 , H04L27/3411
摘要： A mapper for a PAM encoder is provided and includes apparatus for generating desired code levels, and a constellation matrix memory which stores indications of a plurality of different N-dimensional constellations. The plurality of different constellations are used individually or together to support a plurality of different modem data (bit) rates. In order to maximize performance in the presence of robbed bit signalling, multidimensional constellations having different numbers of points are used together in the coding of a single group of bits.
摘要翻译：提供了一种用于PAM编码器的映射器，并且包括用于产生期望代码电平的装置，以及存储多个不同N维星座的指示的星座矩阵存储器。多个不同的星座单独或一起用于支持多个不同的调制解调器数据（比特）速率。为了在存在抢占位信令的情况下最大化性能，具有不同点数的多维星座在一组位的编码中一起使用。

22. 发明授权

US5841773A ATM network switch with congestion level signaling for controlling cell buffers 失效
标题翻译： ATM网络交换机具有用于控制信元缓冲器的拥塞级信令
公开(公告)号：US5841773A
公开(公告)日：1998-11-24
申请号：US644308
申请日：1996-05-10
申请人： Trevor Jones
发明人： Trevor Jones
IPC分类号： H04L12/54 , H04L12/70 , H04L12/933 , H04L12/937 , H04J3/24
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/255 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
摘要： An ATM network switch is provided with a switch fabric linking a plurality of slot controllers. Each slot controller receives ATM cells from an external data link and has at least one input port to the switch fabric. The switch fabric switches a data cell received from any one port to one or more other ports. Each slot controller is provided with a separate group of buffers for each slot controller in the switch, and stores ATM cells intended for those other slot controller in the buffers. Each group of buffers includes a separate buffer for each class of cell traffic, so that the ATM cells are stored by intended slot controller and by class. The slot controller also includes a buffer control circuit which controls the passing of cells from the buffer to the switch fabric. The switch fabric includes input FIFOs, an indication of the fullness of which is measured and signaled back to the buffer control circuit. In response to the feedback signal which is an indication of the congestion level of each switching path through the switch fabric from one port thereto to another, the buffer control circuit controls the output of cells from the slot controller buffers to the switch.
摘要翻译： ATM网络交换机设置有连接多个时隙控制器的交换结构。每个时隙控制器从外部数据链路接收ATM信元，并且具有至少一个到交换结构的输入端口。交换结构将从任何一个端口接收的数据信元切换到一个或多个其他端口。每个时隙控制器为交换机中的每个时隙控制器提供单独的缓冲器组，并且将用于那些其他时隙控制器的ATM信元存储在缓冲器中。每组缓冲器包括用于每类单元流量的单独缓冲器，使得ATM单元由预定的时隙控制器和按类存储。时隙控制器还包括缓冲器控制电路，其控制从缓冲器到交换结构的单元的传递。交换结构包括输入FIFO，其充满度的指示被测量并发送回缓冲器控制电路。响应于反馈信号，其是通过交换结构从一个端口到另一个端口的每个交换路径的拥塞级别的指示，缓冲器控制电路控制从时隙控制器缓冲器到交换机的小区的输出。

23. 发明授权

US5517532A Standing sine wave clock bus for clock distribution systems 失效
标题翻译：用于时钟分配系统的正弦波时钟总线
公开(公告)号：US5517532A
公开(公告)日：1996-05-14
申请号：US143442
申请日：1993-10-26
申请人： Welles Reymond
发明人： Welles Reymond
IPC分类号： G06F1/04 , G06F1/10 , G06F13/40 , H03L7/081 , H04J3/06 , H04L7/00
CPC分类号： H03L7/0812 , G06F1/10 , G06F13/4072 , Y02B60/1228 , Y02B60/1235
摘要： A clock phase and frequency distribution system is disclosed which uses a standing sine wave and provides substantially simultaneous significant crossing instances everywhere in the system while using low power and not requiring bus termination or precise control of transmission path characteristics (Z.sub.0). The system is particularly advantageous in high frequency applications such as digital, linear (non-branched), backplane applications, but is also applicable to other topographies such as stars, rings, and meshes. The system includes a sine wave generating and driving circuit, a clock bus, and clock receivers. The clock receivers present a high impedance interface to the clock bus. The basic design considerations and parameters which limit and define performance include the maximum propagation delay between any two points in the system, the total low frequency capacitance of the system, and the Q of the system which must be high at the frequency of the standing wave in order to satisfy low power and simultaneity objectives. To overcome system length limitations, embodiments utilizing master and slaves are provided, where phase feedback is provided to the slaves. Multifrequency systems are also provided.
摘要翻译：公开了一种时钟相位和频率分配系统，其使用站立正弦波，并且在使用低功率并且不需要总线终端或传输路径特性（Z0）的精确控制）的同时在系统中的每个处提供基本上同时的显着交叉实例。该系统在诸如数字，线性（非分支）背板应用的高频应用中特别有利，但也适用于诸如恒星，环和网格之类的其他形貌。该系统包括正弦波产生和驱动电路，时钟总线和时钟接收器。时钟接收器对时钟总线提供高阻抗接口。限制和定义性能的基本设计注意事项和参数包括系统中任意两个点之间的最大传播延迟，系统的总体低频电容以及驻波频率必须高的系统的Q 以满足低功率和同时性目标。为了克服系统长度限制，提供了利用主机和从机的实施例，其中向从机提供相位反馈。还提供多频系统。

24. 发明授权

US5486825A Convolutional encoders for modems which implement the "Cole code" 失效
标题翻译：实现“科尔码”的调制解调器的卷积编码器
公开(公告)号：US5486825A
公开(公告)日：1996-01-23
申请号：US230682
申请日：1994-04-20
申请人： Paul D. Cole
发明人： Paul D. Cole
IPC分类号： H03M13/25 , H04L25/497 , H04L27/34 , H03M7/00
CPC分类号： H03M13/235 , H03M13/25 , H03M13/256 , H04L25/497 , H04L27/3438
摘要： A sixty-four state convolutional code known as the "Cole code" is disclosed and take systematic and non-systematic forms. The state variables of the Cole code are r(n-1), r(n-2), s(n-1), s(n-2), p(n-1), and x(n-1). In the four-to-five non-systematic form, four inputs p(n), q(n), r(n) and s(n) are used to generate five outputs y.sub.4 (n), y.sub.3 (n), y.sub.2 (n), y.sub.1 (n), and y.sub.0 (n) according to: y.sub.4 (n)=q(n); y.sub.3 (n)=p(n)+r(n)r(n-1)+r(n-2)+r(n-1)s(n)+r(n-1)s(n-2); y.sub.2 (n)=r(n-1)+s(n)+s(n-2); y.sub.1 (n)=r(n)+r(n-1)r(n-2)+p(n-1)+p(n-2)+q(n-1); and y.sub.0 (n)=s(n-1), where p(n-2)+q(n-1)=x(n-1). New state variables are obtained directly from the inputs and from the previous state variables, except for x(n) which is equals q(n)+p(n-1). In a three-to-four non-systematic implementation of the Cole code, q(n) is not input, y.sub.4 is not output, and q(n-1) is set equal to zero. In the four-to-five systematic form of the Cole code, the inputs y.sub.4, y.sub.3, y.sub.2, y.sub.1 are taken as outputs and are also used on conjunction with the convolutional encoder to generate a fifth output y.sub.0. With state variables x(n-1), p(n-1), r(n-1), r(n-2), s(n-1), s(n-2) relabled as w.sub.1, w.sub.2, w.sub.3, w.sub.4, w.sub.5, and w.sub.6, output y.sub.0 is taken as state variable w.sub.5. The state variables are updated according to: new w.sub.6 =w.sub.5 ; new w.sub.5 =y.sub.2 +w.sub.3 +w.sub.6 ; new w.sub.4 =w.sub.3 ; new w.sub.3 =y.sub.1 +w.sub.3 w.sub.4 +w.sub.2 +w.sub.1 ; new w.sub.2 =y.sub.3 +(new w.sub.3)w.sub.3 +w.sub.4 +w.sub.3 (new w.sub.5)+w.sub.3 w.sub.6 ; and new w.sub.1 =y.sub.4 +w.sub.2. In the three-to-four systematic Cole code, y.sub.4 is taken as zero.
摘要翻译：被公认为“科尔码”的64个国家卷积码被公开并采取系统和非系统的形式。科尔码的状态变量是r（n-1），r（n-2），s（n-1），s（n-2），p（n-1）和x（n-1）。在四到五个非系统形式中，使用四个输入p（n），q（n），r（n）和s（n）来生成五个输出y4（n），y3（n），y2 （n），y1（n）和y0（n）根据：y4（n）= q（n）; y（n）=（n）+ r（n）r（n-1）+ r（n-2）+ r（n-1））; y2（n）= r（n-1）+ s（n）+ s（n-2）; y（n）= r（n）+ r（n-1）r（n-2）+ p（n-1）+ p（n-2）+ q（n-1）和y（n）= s（n-1），其中p（n-2）+ q（n-1）= x（n-1）。除了x（n）等于q（n）+ p（n-1）之外，新的状态变量直接从输入和先前的状态变量获得。在Cole码的三到四个非系统实现中，不输入q（n），不输出y4，并且将q（n-1）设置为等于零。在Cole码的四到五个系统形式中，将输入y4，y3，y2，y1作为输出，并且也与卷积编码器结合使用以产生第五输出y0。使用状态变量x（n-1），p（n-1），r（n-1），r（n-2），s（n-1），s（n-2） w3，w4，w5和w6，将输出y0作为状态变量w5。状态变量根据：new w6 = w5; new w5 = y2 + w3 + w6; 新w4 = w3; new w3 = y1 + w3w4 + w2 + w1; new w2 = y3 +（new w3）w3 + w4 + w3（new w5）+ w3w6; 和新的w1 = y4 + w2。在三到四个系统的科尔码中，y4取为零。

25. 发明授权

US5426698A Transformed current sensing relay for use in switched network modems and circuit incorporating same 失效
标题翻译：转换电流检测继电器用于交换网络调制解调器和并入其的电路
公开(公告)号：US5426698A
公开(公告)日：1995-06-20
申请号：US64460
申请日：1993-05-11
申请人： Welles K. Reymond
发明人： Welles K. Reymond
IPC分类号： H01H51/28 , H04M1/82 , H01H51/00
CPC分类号： H01H51/282 , H04M1/82
摘要： A transformed current sensing relay with reduced AC impedance of the operating coil is accomplished by adding a shorted secondary winding to an otherwise conventional current sensing reed relay. The shorted secondary winding is preferably implemented with a copper tube over the existing coil and inside the magnetic circuit. This transformed current sensing relay is particularly advantageous for the line current sensing function in switched network communications equipment such as high speed modems, where the transformed relay exhibits substantially lower impedance at high frequencies than the conventional current sensing relay. This transformed current sensing relay allows for the elimination of bypass capacitors and results in significant cost and space savings. Moreover, the transformer nature of the transformed current sensing relay allows for the elimination of suppression resistors from the interface resulting in additional cost and space savings.
摘要翻译：通过将短路次级绕组添加到另外传统的电流感测簧片继电器来实现具有减小的工作线圈的AC阻抗的变换的电流感测继电器。短路次级绕组优选地在现有线圈和磁路内部用铜管实现。这种变换的电流感测继电器对于诸如高速调制解调器的交换网络通信设备中的线路电流感测功能是特别有利的，其中变换的继电器在高频下表现出比常规电流感测继电器显着更低的阻抗。这种转换的电流感测继电器允许消除旁路电容器，并导致显着的成本和空间节省。此外，变换电流检测继电器的变压器特性允许从接口消除抑制电阻，从而节省额外的成本和空间。

26. 发明授权

US5317594A Systems for and method of identifying V.fast modem within existing automatic interworking procedure standards 失效
标题翻译：在现有的自动交互过程标准中识别V.fast调制解调器的系统和方法
公开(公告)号：US5317594A
公开(公告)日：1994-05-31
申请号：US819277
申请日：1992-01-13
申请人： Yuri Goldstein
发明人： Yuri Goldstein
IPC分类号： H04M11/06 , H04B1/38 , H04L5/16
CPC分类号： H04M11/06
摘要： A method for identifying a V.fast modem within already standard automatic interworking procedures are provided. The method comprises utilizing standard methods for identifying a V.32/V.32bis modem up and through the standard ranging sequence, and after ranging and during the undefined 8192 baud period before an S signal would be sent by a V.32 or V.32bis modem the answering mode modem sends a predetermined signal (VFS) which does not resemble an S signal. Simultaneous with the answer modem sending VFS, the call mode modem looks for VFS. Upon detecting VFS, the call mode modem confirms receipt by sending a confirming signal (VFC) to the answer mode modem. Upon receiving VFC, if the communicating modems are not already in a problem mode, the modems will probe the line and continue according to whatever V.fast standards will be adopted. Preferably, VFS contains at least two tones. If desired, VFS can be a spectrum, with energy in frequency bands surrounding the S tone frequencies suppressed. This way, the VFS signal can be used by the answering modem for probing the line. Similarly, the confirming signal may be one or more tones, or a spectrum of frequencies for probing.
摘要翻译：提供了一种用于在已经标准的自动互通过程中识别V.fast调制解调器的方法。该方法包括利用标准方法来识别V.32 / V.32bis调制解调器，并通过标准测距序列，以及测距之后和未定义的8192波特周期之前，通过V.32或V发送S信号。 32bis调制解调器，应答模式调制解调器发送不类似于S信号的预定信号（VFS）。与应答调制解调器发送VFS同时，呼叫模式调制解调器寻找VFS。在检测VFS时，呼叫模式调制解调器通过向应答模式调制解调器发送确认信号（VFC）确认接收。一旦接收到VFC，如果通信调制解调器尚未处于问题模式，调制解调器将根据将采用的任何VISA标准进行探测并继续。优选地，VFS包含至少两个音调。如果需要，VFS可以是频谱，其中围绕S音频频率的频带中的能量被抑制。这样，VFS信号可以由应答调制解调器用于探测线路。类似地，确认信号可以是一个或多个音调，或用于探测的频率频谱。

27. 发明授权

US4961138A System and apparatus for providing three dimensions of input into a host processor 失效
标题翻译：用于向主处理器提供三维输入的系统和装置
公开(公告)号：US4961138A
公开(公告)日：1990-10-02
申请号：US418694
申请日：1989-10-02
申请人： Andrew M. Gorniak
发明人： Andrew M. Gorniak
IPC分类号： G06F3/038
CPC分类号： G06F3/038 , G06F3/03542 , G06F3/03543 , G06F3/03545
摘要： A system under the hand held control of a user for providing three dimensions of input to a computer processor while operating on an essentially planar surface is disclosed. The system of the invention generally comprises: an apparatus operated over a substantially planar surface; a means chosen from one of a means for detecting and measuring movement of the apparatus in two perpendicular dimensions along the substantially planar surface and a means for determining the location of the apparatus in two perpendicular dimensions along the substantially planar surface, and for providing first outputs representative of either the two-dimensional location or the movement of the apparatus; means for detecting and measuring an analog third dimension input into the apparatus under the control of the user while the apparatus is located along the planar surface, and for providing a second output representative of the third dimension input; and means for receiving the first outputs and the second output and providing therefrom information suitable for input into the computer processor, wherein the information is representative of the three dimensions of input. The apparatus of the system can take various forms such as a computer mouse, a stylus for a bit pad, or a light pen.
摘要翻译：公开了在基本上平坦的表面上操作的同时在用户手中控制用于提供三维输入到计算机处理器的系统。本发明的系统通常包括：在基本平坦的表面上操作的设备; 从沿着基本上平坦的表面的两个垂直尺寸中检测和测量装置的运动的装置之一选择的装置和用于沿着基本平坦的表面确定两个垂直尺寸的装置的位置的装置，以及用于提供第一输出代表设备的二维位置或运动; 用于在所述设备沿着所述平面表面定位并且用于提供代表所述第三尺寸输入的第二输出时，用于在所述用户的控制下检测和测量到所述设备中的模拟第三维输入的装置; 以及用于接收第一输出和第二输出并从其提供适合于输入到计算机处理器的信息的装置，其中该信息代表输入的三个维度。系统的装置可以采用各种形式，例如计算机鼠标，用于位垫的触针或光笔。

28. 发明授权

US4888770A Algorithm for selecting channels for multiplexer frame 失效
标题翻译：选择多路复用帧通道的算法
公开(公告)号：US4888770A
公开(公告)日：1989-12-19
申请号：US259856
申请日：1988-10-19
申请人： Kuldip S. Bains
发明人： Kuldip S. Bains
IPC分类号： H04J3/16
CPC分类号： H04J3/1682
摘要： An algorithm for ordering selects for a plurality of channels to be multiplexed into a frame is provided. A channel ready counter and a channel select position counter for each of the channels to be multiplexed are initialized. The first and succeeding channel selects are chosen based primarily on the respective values of the channel ready counters such that a channel having a ready counter of relative higher value is always selected before a channel having a ready counter of relative lower value. Where channel ready counter integer values of more than one channel are equal, the select is chosen on the secondary basis of channel rate, with the highest rate channel of the highest ready count contributing first. After a select is made, the ready counter of the selected channel is determined, and the position counters of the channels are decremented by a value corresponding to the number of selects for that channel in the frame. If the position counter of a channel reach zero or goes negative as a result of the decrementing, the position counter of that channel is increased by the total number of selects in the frame, and the ready counter for that channel is incremented by one. After such updating, another selection for the frame may be made based on the ready counter values of the channels. The provided algorithm guarantees that no channel will ever have an excursion of more than one bit available for placement in the frame.
摘要翻译：提供了一种用于排序的多路复用通道的选择算法。初始化要复用的每个信道的信道准备计数器和信道选择位置计数器。主要基于通道就绪计数器的相应值选择第一和后续通道选择，使得在具有相对较低值的准备计数器的通道之前总是选择具有相对较高值的准备计数器的通道。在多于一个通道的通道就绪计数器整数值相等的情况下，在通道速率的次要基础上选择选择，最高准备计数的最高速率通道首先起作用。在进行选择之后，确定所选频道的就绪计数器，并且将通道的位置计数器减少与帧中该通道的选择次数对应的值。如果通道的位置计数器由于递减而达到零或变为负值，则该通道的位置计数器将增加帧中的选择总数，并将该通道的就绪计数器增加1。在这种更新之后，可以基于通道的准备好的计数器值来进行该帧的另一选择。所提供的算法保证没有通道将不会有超过一位可用于放置在帧中的偏移。

29. 发明授权

US4845735A Non-interfering method for measuring propagation delay of telecommunications network and apparatus for accomplishing same 失效
标题翻译：用于测量电信网络传播延迟的无干扰方法及其实现方法
公开(公告)号：US4845735A
公开(公告)日：1989-07-04
申请号：US206514
申请日：1988-06-14
申请人： Nicholas W. P. Payne , Kiran K. Mistry
发明人： Nicholas W. P. Payne , Kiran K. Mistry
IPC分类号： H04B3/46 , H04J3/06
CPC分类号： H04B3/462 , H04J3/0682
摘要： Methods and apparatus for measuring propagation delay over a line without interfering with data communications over the line are disclosed. A known signal is sent and looped back over a secondary channel, and the loop time is measured. Because the known signal is sent at a non-interfering frequency at the edge of the passband, the loop time minus fixed delay times of the communicating means does not provide a true measure of propagation delay. Rather, the envelope delay distortion must be determined and also subtracted from the loop time. The envelope delay distortion is determined as a function of the utilized non-interfering frequency and the line length, the latter of which may be estimated from the loop time.

30. 发明授权

US4729123A Method for establishing and maintaining synchronization between communicating multiplexers using checksum values 失效
标题翻译：使用校验和值建立和维持通信多路复用器之间的同步的方法
公开(公告)号：US4729123A
公开(公告)日：1988-03-01
申请号：US896259
申请日：1986-08-14
申请人： Andrew J. T. Wheen
发明人： Andrew J. T. Wheen
IPC分类号： H04L7/04 , H04J3/06
CPC分类号： H04L7/048
摘要： Methods for establishing and maintaining synchronization between communicating multiplexers are provided, wherein a first multiplexer having a frame format multiplexes at least data according to the frame format, and wherein the second multiplexer demultiplexes at least said data according to the frame format, and synchronization is established by: providing the frame format with bit positions for a plurality of bits including first predetermined bit positions for a plurality of checksum bits, and second predetermined bit positions for bits other than checksum bits; calculating a checksum for the bit values of bits located at said second predetermined bit positions, and inserting bits representing the said calculated checksum into said first predetermined bit positions; sending bits including bits located at said first and second predetermined bit positions in said frame format from said first multiplexer to said second multiplexer; and establishing synchronization between said first and second multiplexers by using said bits representing said calculated checksum.In establishing synchronization, the second multiplexer chooses an arbitrary bit as the first bit in the frame. Received bits located at distances from the first bit which are equivalent to the second predetermined bit positions are then used to calculate a checksum. Bits are then located at distances from the first bit which are equivalent to the predetermined first positions. If the checksum calculations do not correspond to the found checksum bits, frame synchronization is not established. The process is then repeated starting with the next bit after the arbitrary point, and continued until the calculated checksum agrees with the bits at the checksum locations.
摘要翻译：提供了用于建立和维持通信多路复用器之间的同步的方法，其中具有帧格式的第一多路复用器至少根据帧格式复用数据，并且其中第二多路复用器至少根据帧格式解复用所述数据，并且建立同步通过：为包括用于多个校验和位的第一预定位位置的多个位的位位置提供帧格式，以及用于除校验和位之外的位的第二预定位位置; 计算位于所述第二预定位位置的位的位值的校验和，并将表示所述计算的校验和的位插入所述第一预定位位置; 将位于位于所述帧格式的所述第一和第二预定位位置的位从所述第一多路复用器发送到所述第二多路复用器; 以及通过使用表示所述计算的校验和的所述比特来在所述第一和第二多路复用器之间建立同步。在建立同步时，第二多路复用器选择任意位作为帧中的第一位。然后使用位于距离第一位的距离等于第二预定位位置的接收位来计算校验和。然后位置与第一位的距离相等于预定的第一位置。如果校验和计算不对应于找到的校验和位，则不会建立帧同步。然后，该过程从任意点之后的下一个比特开始重复，并且一直持续到计算的校验和与校验和位置处的位一致。

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