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    • 21. 发明授权
    • Method and apparatus for measuring magnetic parameters of magnetic thin film structures
    • 用于测量磁性薄膜结构磁参数的方法和装置
    • US08633720B2
    • 2014-01-21
    • US13134925
    • 2011-06-21
    • Ioan TudosaYuchen ZhouJing ZhangRajiv Yadav RanjanYiming Huai
    • Ioan TudosaYuchen ZhouJing ZhangRajiv Yadav RanjanYiming Huai
    • G01R27/08
    • G01R33/093
    • High-frequency resonance method is used to measure magnetic parameters of magnetic thin film stacks that show magnetoresistance including MTJs and giant magnetoresistance spin valves. The thin film sample can be unpatterned. Probe tips are electrically connected to the surface of the film (or alternatively one probe tip can be punched into the thin film stack) and voltage measurements are taken while injecting high frequency oscillating current between them to cause a change in electrical resistance when one of the layers in the magnetic film stack changes direction. A measured resonance curve can be determined from voltages at different current frequencies. The damping, related to the width of the resonance curve peak, is determined through curve fitting. In embodiments of the invention a variable magnetic field is also applied to vary the resonance frequency and extract the magnetic anisotropy and/or magnetic saturation of the magnetic layers.
    • 高频共振法用于测量显示包括MTJs和巨磁阻自旋阀在内的磁阻的磁性薄膜叠层的磁参数。 薄膜样品可以无图案化。 探针尖端电连接到膜的表面(或者可选地,一个探针尖端可以冲压到薄膜堆叠中)并且在其间注入高频振荡电流时进行电压测量,以在其中的一个 磁膜堆中的层改变方向。 可以从不同电流频率的电压确定测得的谐振曲线。 通过曲线拟合确定与共振曲线峰的宽度相关的阻尼。 在本发明的实施例中,还应用可变磁场来改变谐振频率并提取磁性层的磁各向异性和/或磁饱和。
    • 22. 发明申请
    • MRAM Fabrication Method with Sidewall Cleaning
    • MRAM制造方法与侧壁清洁
    • US20130267042A1
    • 2013-10-10
    • US13443818
    • 2012-04-10
    • Kimihiro SatohYiming HuaiYuchen ZhouJing ZhangDong Ha JungEbrahim AbedifardRajiv Yadav RanjanParviz Keshtbod
    • Kimihiro SatohYiming HuaiYuchen ZhouJing ZhangDong Ha JungEbrahim AbedifardRajiv Yadav RanjanParviz Keshtbod
    • H01L21/02
    • H01L27/222H01L43/12
    • Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.
    • 描述了用于MRAM的制造方法,其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中,首先制造柱,然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属,因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样,在侧壁被蚀刻清洁之后,进行位线互连处理。
    • 26. 发明申请
    • Mram etching processes
    • 摩擦蚀刻工艺
    • US20130052752A1
    • 2013-02-28
    • US13199490
    • 2011-08-30
    • Kimihiro SatohYiming HuaiJing ZhangRajiv Yadav RanjanParviz KeshtbodRoger K. Malmhall
    • Kimihiro SatohYiming HuaiJing ZhangRajiv Yadav RanjanParviz KeshtbodRoger K. Malmhall
    • H01L21/8246
    • H01L43/12H01L29/00
    • Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.
    • 本发明的各种实施例涉及用于制造MRAM装置中的MTJ电池的蚀刻工艺。 各种实施例可以彼此组合使用。 第一实施例在硬掩模和顶电极之间添加硬掩模缓冲层。 第二实施例使用多层蚀刻硬掩模。 第三实施例使用包括第二层如Ta之下的第一Cu层的多层顶电极结构。 第四实施例是用于底部电极去除再沉积材料同时保持更垂直侧壁蚀刻轮廓的两相蚀刻工艺。 在第一阶段中,使用碳质反应离子蚀刻去除底部电极层直到端点。 在第二阶段中,使用惰性气体和/或氧等离子体去除在先前蚀刻工艺期间沉积的聚合物。