专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06333645B1 Clocked logic gate circuit 有权
公开(公告)号：US06333645B1
公开(公告)日：2001-12-25
申请号：US09659541
申请日：2000-09-11
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/1738
摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

22. 发明申请

US20080072095A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080072095A1
公开(公告)日：2008-03-20
申请号：US11936543
申请日：2007-11-07
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

23. 发明授权

US07233045B2 Semiconductor device and system 有权
公开(公告)号：US07233045B2
公开(公告)日：2007-06-19
申请号：US10960985
申请日：2004-10-12
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H01L23/62
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.

24. 发明申请

US20050111265A1 Semiconductor device using SCL circuit 失效
标题翻译：半导体器件采用SCL电路
公开(公告)号：US20050111265A1
公开(公告)日：2005-05-26
申请号：US11023395
申请日：2004-12-29
申请人： Kazuo Kanetani , Hiroaki Nambu
发明人： Kazuo Kanetani , Hiroaki Nambu
IPC分类号： G11C11/413 , G11C8/10 , G11C11/34 , H03K19/096 , G11C5/00
CPC分类号： G11C8/10
摘要： It is an object of the invention to provide a circuit configuration wherein a decoder control signal Φ2 is rendered unnecessary between an address buffer control signal Φ1 and the decoder control signal Φ2, thereby implementing speed-up in operation of a decoder circuit. The object is attained by adoption of a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.
摘要翻译：本发明的目的是提供一种电路配置，其中在地址缓冲器控制信号Phi 1和解码器控制信号Phi 2之间不需要解码器控制信号Phi 2，从而在解码器电路的操作中实现加速。该目的通过采用其中缓冲器与解码器集成的配置来实现，使得组成地址缓冲器的晶体管的输出电流路径和构成解码器的晶体管的输出电流路径彼此串联连接，从而形成解码器输出的输出电流路径。利用本发明，可以实现解码器电路的操作加速，低功耗和更高的周期。此外，在使用半导体存储器中的解码器电路的情况下，可以参考半导体存储器来实现访问时间的缩短，低功耗和更高的周期。

25. 发明授权

US06842394B2 Semiconductor device using SCL circuit 失效
标题翻译：半导体器件采用SCL电路
公开(公告)号：US06842394B2
公开(公告)日：2005-01-11
申请号：US10261583
申请日：2002-10-02
申请人： Kazuo Kanetani , Hiroaki Nambu
发明人： Kazuo Kanetani , Hiroaki Nambu
IPC分类号： G11C11/413 , G11C8/10 , G11C11/34 , H03K19/096 , G11C8/00
CPC分类号： G11C8/10
摘要： A high-speed, reduced power consumption address decoder circuit, wherein a decoder control signal Φ2 is rendered unnecessary between an address buffer control signalΦ1 and the decoder control signal Φ2, thereby implementing speed-up in operation of a decoder circuit. Improved speed and reduced power consumption are attained by a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.
摘要翻译：一种高速，低功耗地址解码器电路，其中在地址缓冲器控制信号Phi1和解码器控制信号Phi2之间不需要解码器控制信号Phi2，从而在解码器电路的操作中实现加速。通过将缓冲器与解码器集成而构成地址缓冲器的晶体管的输出电流路径和组成解码器的晶体管的输出电流路径串联连接，可以实现提高速度和降低功耗，从而形成解码器输出的输出电流路径。利用本发明，可以实现解码器电路的操作加速，低功耗和更高的周期。此外，在使用半导体存储器中的解码器电路的情况下，可以参考半导体存储器来实现访问时间的缩短，低功耗和更高的周期。

26. 发明授权

US07685455B2 Semiconductor integrated circuit which generates internal clock signal for fetching input data synchronously with the internal clock signal without decrease of timing margin 有权
标题翻译：半导体集成电路产生内部时钟信号，用于与内部时钟信号同步地提取输入数据，而不会减少定时裕度
公开(公告)号：US07685455B2
公开(公告)日：2010-03-23
申请号：US11936543
申请日：2007-11-07
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/04
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

27. 发明申请

US20070236844A1 Semiconductor device and system 审中-公开
标题翻译：半导体器件和系统
公开(公告)号：US20070236844A1
公开(公告)日：2007-10-11
申请号：US11808083
申请日：2007-06-06
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.
摘要翻译：这里公开了一种改进的半导体器件，用于防止在其中使用的每个MOSFET中可能发生的耐受电压缺陷，以及容易设计的系统，并防止其中可能发生的每个半导体中可能发生的耐电压缺陷。该系统包括第一和第二输入电路，每个由相同工艺制造的MOSFET构成。第一输入电路接收从第一外部端子输入并由第一和第二电阻器装置分压的第一信号的电压，同时输入信号的AC分量通过与第一电阻器平行设置的电容器传输到输入电路。第二输入电路接收从第二外部端子输入的第二输入信号，并减小信号幅度，使其变得小于第一输入信号的输入信号。该系统还包括对应于第一输入电路的第二半导体器件和对应于第二输入电路的第三半导体器件。

28. 发明申请

US20050063112A1 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US20050063112A1
公开(公告)日：2005-03-24
申请号：US10960985
申请日：2004-10-12
申请人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
发明人： Takemi Negishi , Hiroaki Nambu , Kazuo Kanetani , Hideto Kazama
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H03K19/003 , H03K19/0175 , H02H9/00
CPC分类号： H01L27/0251 , H01L27/0259 , H01L2924/0002 , H03K19/00315 , H01L2924/00
摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.
摘要翻译：这里公开了一种改进的半导体器件，用于防止在其中使用的每个MOSFET中可能发生的耐受电压缺陷，以及容易设计的系统，并防止其中可能发生的每个半导体中可能发生的耐电压缺陷。该系统包括第一和第二输入电路，每个由相同工艺制造的MOSFET构成。第一输入电路接收从第一外部端子输入并由第一和第二电阻器装置分压的第一信号的电压，同时输入信号的AC分量通过与第一电阻器平行设置的电容器传输到输入电路。第二输入电路接收从第二外部端子输入的第二输入信号，并减小信号幅度，使其变得小于第一输入信号的输入信号。该系统还包括对应于第一输入电路的第二半导体器件和对应于第二输入电路的第三半导体器件。

29. 发明授权

US07296173B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07296173B2
公开(公告)日：2007-11-13
申请号：US10768441
申请日：2004-02-02
申请人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
发明人： Hiroaki Nambu , Masao Shinozaki , Kazuo Kanetani , Hideto Kazama
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G11C11/413 , G06F1/04 , G11C11/419
摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.
摘要翻译：提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

30. 发明授权

US06954401B2 Semiconductor memory device integrating source-coupled-logic (SCL) circuit into an address buffer and a decoder 失效
标题翻译：将源极耦合逻辑（SCL）电路集成到地址缓冲器和解码器中的半导体存储器件
公开(公告)号：US06954401B2
公开(公告)日：2005-10-11
申请号：US11023395
申请日：2004-12-29
申请人： Kazuo Kanetani , Hiroaki Nambu
发明人： Kazuo Kanetani , Hiroaki Nambu
IPC分类号： G11C11/413 , G11C8/10 , G11C11/34 , H03K19/096 , G11C8/18 , H03K19/20
CPC分类号： G11C8/10
摘要： It is an object of the invention to provide a circuit configuration wherein a decoder control signal Φ2 is rendered unnecessary between an address buffer control signal Φ1 and the decoder control signal Φ2, thereby implementing speed-up in operation of a decoder circuit. The object is attained by adoption of a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.
摘要翻译：本发明的目的是提供一种电路配置，其中在地址缓冲器控制信号Phi 1和解码器控制信号Phi 2之间不需要解码器控制信号Phi 2，从而在解码器电路的操作中实现加速。该目的是通过采用其中缓冲器与解码器集成的配置来实现的，使得构成地址缓冲器的晶体管的输出电流路径和构成解码器的晶体管的输出电流路径彼此串联连接，从而形成解码器输出的输出电流路径。利用本发明，可以实现解码器电路的操作加速，低功耗和更高的周期。此外，在使用半导体存储器中的解码器电路的情况下，可以参考半导体存储器来实现访问时间的缩短，低功耗和更高的周期。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式