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21. 发明申请

US20110157116A1 DISPLAY DEVICE 审中-公开
标题翻译：显示设备
公开(公告)号：US20110157116A1
公开(公告)日：2011-06-30
申请号：US13059161
申请日：2009-06-09
申请人： Ichiro Shiraki , Kazuhiro Maeda , Hiroaki Sugiyama
发明人： Ichiro Shiraki , Kazuhiro Maeda , Hiroaki Sugiyama
IPC分类号： G06F3/038
CPC分类号： G09G3/3648 , G09G2320/0233 , G09G2360/145 , H01L31/145
摘要： Provided is a display device including a sensor row driver (6) which sequentially outputs a read-out signal (RW) for causing each pair of picture element area groups, which includes both a first picture element area (PIX1) and a second picture element area (PIX2) as detection picture element areas and is made up of two picture element rows, to simultaneously output a photodetection signal of each of the first picture element areas (PIX1) and a dark current detection signal of each of the second picture element areas (PIX2). In each pair of the picture element area groups, outputs of the detection picture element areas are connected to different output lines (RSL1, RSL2).
摘要翻译：提供了一种显示装置，其包括传感器行驱动器（6），其顺序地输出用于使每对图像元素区域组的读出信号（RW），其包括第一图像元素区域（PIX1）和第二图像元素区域（PIX2）作为检测图像元素区域，并且由两个图像元素行构成，以同时输出第一像素区域（PIX1）中的每一个的每个的第一像素区域和第二像素区域的暗电流检测信号（PIX2）。在每对像素区域组中，检测像素区域的输出连接到不同的输出线（RSL1，RSL2）。

22. 发明申请

US20100231493A1 DISPLAY DEVICE 审中-公开
标题翻译：显示设备
公开(公告)号：US20100231493A1
公开(公告)日：2010-09-16
申请号：US12679108
申请日：2008-05-09
申请人： Yasuyoshi Kaise , Keisuke Yoshida , Kazuhiro Maeda
发明人： Yasuyoshi Kaise , Keisuke Yoshida , Kazuhiro Maeda
IPC分类号： G09G3/36
CPC分类号： G02F1/136213 , G02F1/133371 , G02F1/13338 , G02F1/136286 , G02F2201/40 , G06F3/0412
摘要： The present invention relates to a display device capable of improving display qualities.The present invention is a display device including: pixels arrayed in a matrix pattern in n-rows and m-columns (n and m being each an integer of 2 or more); n-source lines; and m-gate lines, the n-source lines and the m-gate lines being arranged in a lattice pattern, wherein a configuration of a pixel in an odd-numbered row of the n-rows and a configuration of a pixel in an even-numbered row of the n-rows are in an inverse relationship, the display device further includes a storage capacitor wiring shared between the pixel in the odd-numbered row and the pixel in the even-numbered row, the storage capacitor wiring is arranged in a boundary region between the pixel in the odd-numbered row and the pixel in the even-numbered row, and the storage capacitor wiring faces a storage capacitor electrode for the pixel in the odd-numbered row and a storage capacitor electrode for the pixel in the even-numbered row, each with an insulating film therebetween.
摘要翻译：本发明涉及能够提高显示质量的显示装置。本发明是一种显示装置，包括：以n行m列排列成矩阵状的像素（n和m为2以上的整数）。 n源线 n栅极线和m栅极线配置成格子图案，其中n行奇数行中的像素的构造和偶数像素的构造 n行的直列为反向关系，显示装置还包括在奇数行中的像素与偶数行中的像素之间共享的存储电容布线，辅助电容布线布置在奇数行中的像素与偶数行中的像素之间的边界区域和辅助电容布线面对用于奇数行中的像素的辅助电容电极和用于像素的存储电容器电极偶数行，其间具有绝缘膜。

23. 发明申请

US20100033458A1 Buffer circuit having voltage switching function, and liquid crystal display device 审中-公开
标题翻译：具有电压切换功能的缓冲电路和液晶显示装置
公开(公告)号：US20100033458A1
公开(公告)日：2010-02-11
申请号：US12311978
申请日：2007-07-05
申请人： Shinsaku Shimizu , Kazuhiro Maeda , Ichiro Shiraki
发明人： Shinsaku Shimizu , Kazuhiro Maeda , Ichiro Shiraki
IPC分类号： G09G5/00 , H03K17/00
CPC分类号： H03K5/08 , G09G3/3614 , G09G3/3688 , G09G3/3696 , G09G2310/027 , G09G2310/0291 , H03K5/22
摘要： In one embodiment of the invention, a capacitor is provided between a node and a negative-side input terminal of a differential amplifier. A switch SW11 is provided between the negative-side input terminal and an output terminal of the differential amplifier. A switch SW12 is provided between the node and the output terminal of the differential amplifier. Switches SW13 to SW16 are provided for switching between a voltage of the node and a positive-side input voltage of the differential amplifier. The switches SW11 and SW12 are on during different periods. In a positive polarity mode, the switches SW13 and SW16 are when the switch SW11 is on while the switch SW16 is on when the switch SW12 is on. In a negative polarity mode, the switches SW14 and SW15 are on when the switch SW11 is on while the switch SW16 is on when the switch SW12 is on. Thus, two types of gradation voltages each required for AC drive of a liquid crystal can be generated with a small circuit scale.
摘要翻译：在本发明的一个实施例中，在差分放大器的节点和负侧输入端之间提供电容器。开关SW11设置在差分放大器的负侧输入端子和输出端子之间。开关SW12设置在差分放大器的节点和输出端子之间。提供开关SW13至SW16用于在节点的电压和差分放大器的正侧输入电压之间切换。开关SW11和SW12在不同的周期内接通。在正极性模式中，开关SW13和SW16是当开关SW12导通时开关SW11导通的状态。在负极性模式下，当开关SW12导通时，开关SW11接通时，开关SW14，SW15接通。因此，可以以小的电路规模产生用于液晶的AC驱动所需的两种类型的灰度电压。

24. 发明授权

US07333096B2 Display device and driving method thereof 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US07333096B2
公开(公告)日：2008-02-19
申请号：US10316193
申请日：2002-12-11
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： A control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area is refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译：用于控制向像素PIX写入的控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷，可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时限制功耗。

25. 发明申请

US20070146354A1 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 审中-公开
公开(公告)号：US20070146354A1
公开(公告)日：2007-06-28
申请号：US11634738
申请日：2006-12-05
申请人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

26. 发明授权

US07212184B2 Shift register and image display device 有权
标题翻译：移位寄存器和图像显示设备
公开(公告)号：US07212184B2
公开(公告)日：2007-05-01
申请号：US10800352
申请日：2004-03-12
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0289
摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.
摘要翻译：在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。此外，使用两种时钟信号，每个时钟信号的占空比不大于50％，并且在其低电平时段中没有重叠部分，以便防止移位寄存器的输出与每个其他。因此，可以提供优选用于图像显示装置的驱动电路的移位寄存器，可以使驱动电路小型化，并且可以期望地改变输出信号的脉冲宽度，并且还提供图像显示装置使用这种移位寄存器。

27. 发明授权

US07190338B2 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US07190338B2
公开(公告)日：2007-03-13
申请号：US11091012
申请日：2005-03-25
申请人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G5/00
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

28. 发明授权

US07173598B2 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
公开(公告)号：US07173598B2
公开(公告)日：2007-02-06
申请号：US11063718
申请日：2005-02-22
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

29. 发明授权

US07150341B2 Transmission apparatus of all-terrain vehicle 失效
标题翻译：全地形车辆传动装置
公开(公告)号：US07150341B2
公开(公告)日：2006-12-19
申请号：US10704971
申请日：2003-11-12
申请人： Kazuhiro Maeda , Koji Watanabe
发明人： Kazuhiro Maeda , Koji Watanabe
IPC分类号： B60W10/10 , B60W10/18
CPC分类号： B62K5/01 , B60K37/06 , B60K2350/102 , B62K11/14 , F16H59/02 , F16H2059/0256 , F16H2059/081 , Y10T74/2022 , Y10T74/20262 , Y10T74/20287
摘要： A transmission apparatus of an all-terrain vehicle includes: a non-stage transmission disposed in a power transmission path from an engine to drive wheels; a forward and backward movement switching device capable of switching to a forward movement position, a neutral position, or a backward movement position, the forward and backward movement switching device being disposed in the power transmission path at a position near said engine; and a shift operation device for switching forward and backward movement disposed on a handle bar at a position adjacent to a handle grip, the shift operation device and the forward and backward movement switching device being interlocked with each other.
摘要翻译：全地形车辆的传动装置包括：设置在从发动机到驱动轮的动力传递路径中的非级变速器; 前后运动切换装置，其能够切换到前进运动位置，中立位置或后退位置，所述前后运动切换装置设置在所述动力传递路径中的靠近所述发动机的位置; 以及用于在与手柄相邻的位置处设置在把手上的向前和向后移动的换档操作装置，所述换档操作装置和所述前后移动切换装置彼此互锁。

30. 发明申请

US20060181502A1 Signal line driving circuit and image display device 审中-公开
公开(公告)号：US20060181502A1
公开(公告)日：2006-08-17
申请号：US11402352
申请日：2006-04-11
申请人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
发明人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0289
摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.

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