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21. 发明授权

US06608524B2 Automatic gain control circuit 失效
公开(公告)号：US06608524B2
公开(公告)日：2003-08-19
申请号：US10163456
申请日：2002-06-07
申请人： Akira Kawabe , Kouji Okamoto
发明人： Akira Kawabe , Kouji Okamoto
IPC分类号： H03G320
CPC分类号： H03G3/3084
摘要： In a state where a PLL circuit is not locked, a gain control signal according to the difference between a peak value of a reproduced signal and the upper or lower limit value of the dynamic range of an A/D converter is given to a variable gain amplifier. In a state where the PLL circuit is locked, a gain control signal according to the difference between the reproduced signal and a reference value that corresponds to a level to which the reproduced signal belongs is given to the variable gain amplifier for each sampling point of the A/D converter. The variable gain amplifier amplifies the reproduced signal with a gain according to the gain control signal.

22. 发明授权

US06393084B1 Clock recovery circuit 有权
公开(公告)号：US06393084B1
公开(公告)日：2002-05-21
申请号：US09734183
申请日：2000-12-12
申请人： Kouji Okamoto
发明人： Kouji Okamoto
IPC分类号： H03D324
摘要： An oscillating clock frequency of a VFO (variable frequency oscillator) is controlled, using the results of addition of an output from a constant multiplier and an output from an accumulator, which is a result of accumulation of outputs from another constant multiplier, based on a phase error signal by setting the output from an enable-provided latch to 0 during a frequency pull-in operation. A control signal generating portion outputs a pulse at the Hi level as a control signal when completion of frequency pull-in is detected. The latch stores the output from the constant multiplier at the time when the control signal is supplied. Thus, a phase pull-in operation is started in the state where a latch output representing a frequency correction component is obtained. During the phase pull-in operation, the VFO is controlled using the result of addition of an output from the multiplier, an output from the accumulator and an output from the latch. Thus, high speed phase pull-in can be achieved, for example, in reproducing data signal recorded in a recording medium.

23. 发明申请

US20120081339A1 DIGITAL PLL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND DISPLAY APPARATUS 有权
标题翻译：数字PLL电路，半导体集成电路和显示设备
公开(公告)号：US20120081339A1
公开(公告)日：2012-04-05
申请号：US13313638
申请日：2011-12-07
申请人： Hiroki MOURI , Kouji Okamoto , Fumiaki Senoue
发明人： Hiroki MOURI , Kouji Okamoto , Fumiaki Senoue
IPC分类号： G09G5/00 , H03L7/08
CPC分类号： H03D13/003 , H03L7/087 , H03L2207/50
摘要： In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.
摘要翻译：在数字PLL电路中，相位比较电路对参考时钟和振荡时钟的转换次数进行计数，将所参考时钟的转换次数达到参考计数值所花费的时间设置为相位比较时间段，以及将作为相位误差值的目标计数值相对于基准时钟的频率和基准计数值的期望的振荡频率的倍率值与振荡的转移次数进行比较，时钟在相位比较时间段。平滑电路平滑相位误差值。数字控制振荡电路根据平滑电路平滑的相位误差值来控制振荡时钟的频率。

24. 发明申请

US20110206144A1 RECEIVER AND TRANSMISSION/RECEPTION SYSTEM 审中-公开
标题翻译：接收器和传输/接收系统
公开(公告)号：US20110206144A1
公开(公告)日：2011-08-25
申请号：US13101679
申请日：2011-05-05
申请人： Akira YAMAMOTO , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira YAMAMOTO , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L27/206 , H04L1/0057 , H04L1/206 , H04L27/2332
摘要： In a wireless receiver, a “variance” of an intermediate output signal of a demodulation section is calculated by a variance calculation section, and the calculated variance is used as a signal quality indicator which indicates the degree of goodness of a receiving condition. For example, when the “variance” is small, a gain of a low-noise amplifier is reduced, or an operation clock frequency of a baseband oscillator is reduced, etc. Thus, when the receiving condition indicated by the indicator is good and sufficient performance is ensured, the performance can be slightly lowered to reduce power consumption. The “variance” is a compact indicator which can be calculated using a simple operation, and is used as a new signal quality indicator.
摘要翻译：在无线接收机中，通过方差计算部分计算出解调部分的中间输出信号的“方差”，将所计算出的方差作为表示接收条件良好程度的信号质量指标。例如，当“方差”小时，降低了低噪声放大器的增益，或降低了基带振荡器的操作时钟频率等。因此，当指示符指示的接收条件良好且足够时性能得到保证，性能可以稍微降低以降低功耗。 “方差”是可以使用简单操作计算的紧凑指示器，并且用作新的信号质量指示符。

25. 发明申请

US20110205444A1 RECEIVER, SIGNAL PROCESSING APPARATUS, AND VIDEO DISPLAY APPARATUS 有权
标题翻译：接收器，信号处理装置和视频显示装置
公开(公告)号：US20110205444A1
公开(公告)日：2011-08-25
申请号：US13101654
申请日：2011-05-05
申请人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H04N5/455
CPC分类号： H04N7/163 , G09G5/006 , G09G2330/021 , G09G2340/12 , G09G2370/12 , G09G2370/16 , G09G2370/20 , G09G2370/22 , H04N21/4305 , H04N21/43615 , H04N21/44
摘要： A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.
摘要翻译：一种用于以多个传输方案接收信号的接收机，其成功地减小了其电路尺寸。用于接收基带信号和调制信号的接收机包括：第一PLL电路，被配置为基于与基带信号同步的外部时钟产生第一内部时钟; 解调器，被配置为解调所述调制信号以输出所述解调信号; 选择器，被配置为选择所述基带信号或所述解调信号之一; 以及第一CDR电路，被配置为通过使用第一内部时钟从由选择器选择的信号中产生恢复的时钟和恢复的数据。

26. 发明授权

US07851441B2 Water-soluble elastin, process for producing same, and food and medicine containing same 有权
标题翻译：水溶性弹性蛋白，其制造方法以及含有它们的食品和药物
公开(公告)号：US07851441B2
公开(公告)日：2010-12-14
申请号：US11666443
申请日：2005-10-27
申请人： Kouji Okamoto , Hiroshi Yamada , Iori Maeda
发明人： Kouji Okamoto , Hiroshi Yamada , Iori Maeda
IPC分类号： A61K38/39 , C07K14/78 , C07K1/14
CPC分类号： C07K14/78 , A61K38/00
摘要： A low-molecular-weight water-soluble elastin having a molecular weight of about 10,000 to 30,000 and a high-molecular-weight water-soluble elastin having a molecular weight of about 30,000 to 300,000 are provided, 79% to 84% of the constituent amino acids of the elastin comprising proline, glycine, alanine, and valine, 2% to 3% comprising aspartic acid and glutamic acid, 0.7% to 1.3% comprising lysine, histidine, and arginine, and 0.2% to 0.4% comprising desmosine and isodesmosine. The low-molecular-weight water-soluble elastin that is obtained may be used in a functional food or a medicine. Such a high-purity water-soluble elastin may be produced by obtaining pure insoluble elastin by subjecting animal body tissue to a collagen removal treatment and then fragmenting the insoluble elastin by means of a solubilizing liquid. It may be produced simply, merely by adjusting the concentration of an alkaline solution and the reaction time without recovering insoluble elastin from the animal body tissue.
摘要翻译：提供分子量约为10,000至30,000的低分子量水溶性弹性蛋白和分子量为约30,000至300,000的高分子量水溶性弹性蛋白，79％至84％的成分包含脯氨酸，甘氨酸，丙氨酸和缬氨酸的弹性蛋白的氨基酸，包含天冬氨酸和谷氨酸的2％至3％，包含赖氨酸，组氨酸和精氨酸的0.7％至1.3％的氨基酸，以及包含去肌氨酸和异丝氨酸的0.2％至0.4％。获得的低分子量水溶性弹性蛋白可以用于功能性食品或药物中。这样的高纯度水溶性弹性蛋白可以通过使动物体组织进行胶原去除处理，然后利用增溶液使不溶性弹性蛋白破碎而获得纯不溶性弹性蛋白来制造。仅通过调节碱性溶液的浓度和反应时间就可以简单地制备，而不从动物体组织中回收不溶性弹性蛋白。

27. 发明授权

US07688687B2 Timing extractor, and information playback apparatus and DVD device using the timing extractor 有权
标题翻译：定时提取器，信息播放装置和使用定时提取器的DVD装置
公开(公告)号：US07688687B2
公开(公告)日：2010-03-30
申请号：US11667299
申请日：2006-07-18
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B7/085
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/1403 , G11B2020/1476 , G11B2220/2562 , H03L7/091 , H03L7/1976 , H04L7/02 , H04L7/033
摘要： In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.
摘要翻译：在从再现信号中提取定时信息的前馈定时提取器中，频率比计算部分2通过利用特定的模式和特定的模式来计算重放信号的频率与频率合成器6的输出时钟的频率之间的比率重放信号中的图案出现间隔。控制部分4以频率比计算部分2计算出的频率比具有设定值的方式控制频率合成器6的分频率。因此，与频率合成器6的输出时钟为高频固定速度时钟的情况相比，不需要以高速操作数字电路。因此，即使在信号的重放频率（播放速度）随时间变化的情况下，消除固定时钟的脉冲的抽取率恒定，从而降低功耗。

28. 发明申请

US20100020250A1 REPRODUCED SIGNAL PROCESSOR AND VIDEO DISPLAY 失效
标题翻译：复制信号处理器和视频显示
公开(公告)号：US20100020250A1
公开(公告)日：2010-01-28
申请号：US12526746
申请日：2007-11-01
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
IPC分类号： H04N5/66 , H04N5/95
CPC分类号： H04L7/0331 , G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B20/14 , G11B2020/1287 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562 , H03L7/06
摘要： In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.
摘要翻译：在前馈控制型再现信号处理器中，时钟发生器1根据由数字值发生器7设定的数字值改变时钟频率。因此，优化了系统的功耗并且便于控制。此外，当频率锁定状态被建立，其中由频率比计算器3计算的频率比满足设定条件时，使用时钟发生器1的时钟产生具有小变化的调制分量。因此，数字值为用调制分量更新，使得时钟发生器1的时钟频率的变化逐渐变化。结果，降低了时钟频率的变化对解码处理的响应的影响。

29. 发明申请

US20080169948A1 Filter Adjustment Circuit 有权
标题翻译：过滤器调节电路
公开(公告)号：US20080169948A1
公开(公告)日：2008-07-17
申请号：US11792081
申请日：2005-09-02
申请人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
发明人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
IPC分类号： H03M1/06 , H03H11/04 , H03H11/20 , H03M1/10 , H03H11/12
CPC分类号： H03G5/16 , H03H11/1291 , H03H11/20
摘要： In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2. As a result, variations in the response characteristics of the Gm-C filter 2 are adjusted with high accuracy with a simple circuit structure.
摘要翻译：在用于诸如Gm-C滤波器的模拟滤波器电路的滤波器调节电路中，来自参考信号产生电路1的输入信号IS被输入到要过滤的Gm-C滤波器2，然后由转换电路3转换成数字信号。来自参考信号发生电路1的参考信号RS由转换电路4转换成数字信号。两个转换信号在保持电路5中保持时间序列。定时产生电路6基于来自保持电路5的基准时间序列信号ref产生更新定时信号en。控制信号产生电路7产生控制基于参考时间序列信号ref的信号CS和来自保持电路5的滤波器输出时间序列信号tgt。控制信号CS响应于更新定时信号en至...而被输入到Gm-C滤波器2 调整Gm-C滤波器2的增益。结果，以简单的电路结构，高精度地调整Gm-C滤波器2的响应特性的变化。

30. 发明授权

US07298219B2 Phase-locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US07298219B2
公开(公告)日：2007-11-20
申请号：US11269742
申请日：2005-11-09
申请人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
发明人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
IPC分类号： H03L7/00 , H03L1/02
CPC分类号： H03L7/0995 , H03L7/0898 , H03L7/18 , H03L7/1976
摘要： The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.
摘要翻译：锁相环电路包括用于设定压控振荡器的增益的增益设定电路和用于设定时间常数的时间常数设定电路，时间常数由电荷泵电路中的电流量和电容环路滤波器的值。增益设定电路将增益设定为预定值，时间常数设定电路将时间常数设定为规定值，由此将锁相环电路的环带宽度设定为期望值。

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