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    • 1. 发明申请
    • DIGITAL PLL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND DISPLAY APPARATUS
    • 数字PLL电路,半导体集成电路和显示设备
    • US20120081339A1
    • 2012-04-05
    • US13313638
    • 2011-12-07
    • Hiroki MOURIKouji OkamotoFumiaki Senoue
    • Hiroki MOURIKouji OkamotoFumiaki Senoue
    • G09G5/00H03L7/08
    • H03D13/003H03L7/087H03L2207/50
    • In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.
    • 在数字PLL电路中,相位比较电路对参考时钟和振荡时钟的转换次数进行计数,将所参考时钟的转换次数达到参考计数值所花费的时间设置为相位比较时间段,以及 将作为相位误差值的目标计数值相对于基准时钟的频率和基准计数值的期望的振荡频率的倍率值与振荡的转移次数进行比较, 时钟在相位比较时间段。 平滑电路平滑相位误差值。 数字控制振荡电路根据平滑电路平滑的相位误差值来控制振荡时钟的频率。