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1. 发明申请

US20110206144A1 RECEIVER AND TRANSMISSION/RECEPTION SYSTEM 审中-公开
标题翻译：接收器和传输/接收系统
公开(公告)号：US20110206144A1
公开(公告)日：2011-08-25
申请号：US13101679
申请日：2011-05-05
申请人： Akira YAMAMOTO , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira YAMAMOTO , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L27/206 , H04L1/0057 , H04L1/206 , H04L27/2332
摘要： In a wireless receiver, a “variance” of an intermediate output signal of a demodulation section is calculated by a variance calculation section, and the calculated variance is used as a signal quality indicator which indicates the degree of goodness of a receiving condition. For example, when the “variance” is small, a gain of a low-noise amplifier is reduced, or an operation clock frequency of a baseband oscillator is reduced, etc. Thus, when the receiving condition indicated by the indicator is good and sufficient performance is ensured, the performance can be slightly lowered to reduce power consumption. The “variance” is a compact indicator which can be calculated using a simple operation, and is used as a new signal quality indicator.
摘要翻译：在无线接收机中，通过方差计算部分计算出解调部分的中间输出信号的“方差”，将所计算出的方差作为表示接收条件良好程度的信号质量指标。例如，当“方差”小时，降低了低噪声放大器的增益，或降低了基带振荡器的操作时钟频率等。因此，当指示符指示的接收条件良好且足够时性能得到保证，性能可以稍微降低以降低功耗。 “方差”是可以使用简单操作计算的紧凑指示器，并且用作新的信号质量指示符。

2. 发明申请

US20110205444A1 RECEIVER, SIGNAL PROCESSING APPARATUS, AND VIDEO DISPLAY APPARATUS 有权
标题翻译：接收器，信号处理装置和视频显示装置
公开(公告)号：US20110205444A1
公开(公告)日：2011-08-25
申请号：US13101654
申请日：2011-05-05
申请人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H04N5/455
CPC分类号： H04N7/163 , G09G5/006 , G09G2330/021 , G09G2340/12 , G09G2370/12 , G09G2370/16 , G09G2370/20 , G09G2370/22 , H04N21/4305 , H04N21/43615 , H04N21/44
摘要： A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.
摘要翻译：一种用于以多个传输方案接收信号的接收机，其成功地减小了其电路尺寸。用于接收基带信号和调制信号的接收机包括：第一PLL电路，被配置为基于与基带信号同步的外部时钟产生第一内部时钟; 解调器，被配置为解调所述调制信号以输出所述解调信号; 选择器，被配置为选择所述基带信号或所述解调信号之一; 以及第一CDR电路，被配置为通过使用第一内部时钟从由选择器选择的信号中产生恢复的时钟和恢复的数据。

3. 发明申请

US20100020250A1 REPRODUCED SIGNAL PROCESSOR AND VIDEO DISPLAY 失效
标题翻译：复制信号处理器和视频显示
公开(公告)号：US20100020250A1
公开(公告)日：2010-01-28
申请号：US12526746
申请日：2007-11-01
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
IPC分类号： H04N5/66 , H04N5/95
CPC分类号： H04L7/0331 , G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B20/14 , G11B2020/1287 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562 , H03L7/06
摘要： In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.
摘要翻译：在前馈控制型再现信号处理器中，时钟发生器1根据由数字值发生器7设定的数字值改变时钟频率。因此，优化了系统的功耗并且便于控制。此外，当频率锁定状态被建立，其中由频率比计算器3计算的频率比满足设定条件时，使用时钟发生器1的时钟产生具有小变化的调制分量。因此，数字值为用调制分量更新，使得时钟发生器1的时钟频率的变化逐渐变化。结果，降低了时钟频率的变化对解码处理的响应的影响。

4. 发明授权

US08305493B2 Receiver, signal processing apparatus, and video display apparatus 有权
标题翻译：接收机，信号处理装置和视频显示装置
公开(公告)号：US08305493B2
公开(公告)日：2012-11-06
申请号：US13101654
申请日：2011-05-05
申请人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H03L7/00 , H04N3/27 , H04N5/268
CPC分类号： H04N7/163 , G09G5/006 , G09G2330/021 , G09G2340/12 , G09G2370/12 , G09G2370/16 , G09G2370/20 , G09G2370/22 , H04N21/4305 , H04N21/43615 , H04N21/44
摘要： A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.
摘要翻译：一种用于以多个传输方案接收信号的接收机，其成功地减小了其电路尺寸。用于接收基带信号和调制信号的接收机包括：第一PLL电路，被配置为基于与基带信号同步的外部时钟产生第一内部时钟; 解调器，被配置为解调所述调制信号以输出所述解调信号; 选择器，被配置为选择所述基带信号或所述解调信号之一; 以及第一CDR电路，被配置为通过使用第一内部时钟从由选择器选择的信号中产生恢复的时钟和恢复的数据。

5. 发明授权

US08098972B2 Reproduced signal processor and video display 失效
标题翻译：转载信号处理器和视频显示
公开(公告)号：US08098972B2
公开(公告)日：2012-01-17
申请号：US12526746
申请日：2007-11-01
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
IPC分类号： H04N5/932 , H04N5/935
CPC分类号： H04L7/0331 , G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B20/14 , G11B2020/1287 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562 , H03L7/06
摘要： In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.
摘要翻译：在前馈控制型再现信号处理器中，时钟发生器1根据由数字值发生器7设定的数字值改变时钟频率。因此，优化了系统的功耗并且便于控制。此外，当频率锁定状态被建立，其中由频率比计算器3计算的频率比满足设定条件时，使用时钟发生器1的时钟产生具有小变化的调制分量。因此，数字值为用调制分量更新，使得时钟发生器1的时钟频率的变化逐渐变化。结果，降低了时钟频率的变化对解码处理的响应的影响。

6. 发明申请

US20110095786A1 PHASE COMPARATOR, PLL CIRCUIT, INFORMATION REPRODUCTION PROCESSING DEVICE, OPTICAL DISK PLAYBACK DEVICE AND MAGNETIC DISK PLAYBACK DEVICE 审中-公开
标题翻译：相位比较器，PLL电路，信息再现处理装置，光盘播放装置和磁盘播放装置
公开(公告)号：US20110095786A1
公开(公告)日：2011-04-28
申请号：US12515337
申请日：2008-09-22
申请人： Akira Yamamoto , Yoshinori Shirakawa , Kouji Okamoto , Hiroki Mouri
发明人： Akira Yamamoto , Yoshinori Shirakawa , Kouji Okamoto , Hiroki Mouri
IPC分类号： H03D13/00
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/10425 , G11B20/14 , G11B2220/2537 , H03L7/091 , H04L7/0334
摘要： In a phase comparator used for a sync clock extraction circuit for extracting a clock synchronizing with reproduction data, a zero cross detection section 701, receiving the reproduction data, outputs a rising cross detection signal, a falling cross detection signal and three phase error candidates that are three consecutive samples. Rising and falling reference value hold sections 703 and 704 respectively output rising and falling reference values. When receiving the rising or falling cross detection signal, a phase error calculation section 702 outputs a sample the difference of which from the rising or falling reference value is minimum in absolute value, out of the three samples including a zero cross sample, as a phase error. The phase error is held in the rising or falling reference value hold section 703 or 704 as the rising or falling reference value for the next phase error calculation.
摘要翻译：在用于提取与再现数据同步的时钟的同步时钟提取电路的相位比较器中，接收再现数据的零交叉检测部分701输出上升交叉检测信号，下降交叉检测信号和三相误差候选，是连续三个样本。上升和下降参考值保持部分703和704分别输出上升和下降参考值。当接收到上升或下降的交叉检测信号时，相位误差计算部分702将包含零交叉样本的三个样本中的从上升或下降基准值的差值的绝对值的差值输出为相位错误。相位误差保持在上升或下降基准值保持部分703或704中作为下一个相位误差计算的上升或下降基准值。

7. 发明申请

US20090086588A1 Timing extractor, and information playback apparatus and dvd device using the timing extractor 有权
标题翻译：定时提取器，以及使用定时提取器的信息播放装置和DVD设备
公开(公告)号：US20090086588A1
公开(公告)日：2009-04-02
申请号：US11667299
申请日：2006-07-18
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B21/08
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/1403 , G11B2020/1476 , G11B2220/2562 , H03L7/091 , H03L7/1976 , H04L7/02 , H04L7/033
摘要： In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.
摘要翻译：在从再现信号中提取定时信息的前馈定时提取器中，频率比计算部分2通过利用特定的模式和特定的模式来计算重放信号的频率与频率合成器6的输出时钟的频率之间的比率重放信号中的图案出现间隔。控制部分4以频率比计算部分2计算出的频率比具有设定值的方式控制频率合成器6的分频率。因此，与频率合成器6的输出时钟为高频固定速度时钟的情况相比，不需要以高速操作数字电路。因此，即使在信号的重放频率（播放速度）随时间变化的情况下，消除固定时钟的脉冲的抽取率恒定，从而降低功耗。

8. 发明授权

US07688687B2 Timing extractor, and information playback apparatus and DVD device using the timing extractor 有权
标题翻译：定时提取器，信息播放装置和使用定时提取器的DVD装置
公开(公告)号：US07688687B2
公开(公告)日：2010-03-30
申请号：US11667299
申请日：2006-07-18
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B7/085
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/1403 , G11B2020/1476 , G11B2220/2562 , H03L7/091 , H03L7/1976 , H04L7/02 , H04L7/033
摘要： In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.
摘要翻译：在从再现信号中提取定时信息的前馈定时提取器中，频率比计算部分2通过利用特定的模式和特定的模式来计算重放信号的频率与频率合成器6的输出时钟的频率之间的比率重放信号中的图案出现间隔。控制部分4以频率比计算部分2计算出的频率比具有设定值的方式控制频率合成器6的分频率。因此，与频率合成器6的输出时钟为高频固定速度时钟的情况相比，不需要以高速操作数字电路。因此，即使在信号的重放频率（播放速度）随时间变化的情况下，消除固定时钟的脉冲的抽取率恒定，从而降低功耗。

9. 发明申请

US20110043693A1 SYNCHRONOUS CONTROL CIRCUIT AND VIDEO DISPLAY DEVICE 审中-公开
标题翻译：同步控制电路和视频显示设备
公开(公告)号：US20110043693A1
公开(公告)日：2011-02-24
申请号：US12885838
申请日：2010-09-20
申请人： Hiroyuki Nakahira , Takashi Yamamoto , Kouji Okamoto , Akira Yamamoto
发明人： Hiroyuki Nakahira , Takashi Yamamoto , Kouji Okamoto , Akira Yamamoto
IPC分类号： H04L7/00 , H04N9/475
CPC分类号： H04L7/0337 , G09G5/008 , G09G2370/16 , H03L7/0812 , H04L7/0334
摘要： A synchronization control circuit is provided with a first sampling means for sampling the envelope signal of the modulation signal at a first sampling timing, a second sampling means for sampling the envelope signal at a second sampling timing, a third sampling means for sampling the envelope signal at a third sampling timing, a phase error calculation means for calculating a phase error value indicating the amount of synchronization deviation between the modulation signal and the reference clock signal using the outputs of the first, second, and third sampling means, a delay control means for generating a delay control signal on the basis of the phase error value, and a delay generation means for generating the first, second, and third sampling timing by delaying the reference clock signal based on the delay control signal. Thereby, a synchronization control circuit that can reduce the circuit size required for obtaining the synchronization with relative to the Early/Late system can be provided.
摘要翻译：同步控制电路设置有第一采样装置，用于在第一采样定时对调制信号的包络信号进行采样，第二采样装置用于在第二采样定时采样包络信号;第三采样装置，用于对包络信号进行采样在第三采样定时，使用相位误差计算装置，用于使用第一，第二和第三采样装置的输出来计算指示调制信号和参考时钟信号之间的同步偏差量的相位误差值;延迟控制装置用于基于相位误差值产生延迟控制信号;以及延迟产生装置，用于通过基于延迟控制信号延迟参考时钟信号来产生第一，第二和第三采样定时。因此，可以提供能够相对于Early / Late系统减小获得同步所需的电路尺寸的同步控制电路。

10. 发明申请

US20130130384A1 TEMPERATURE RESPONSIVE SHEET THAT DISPLAYS REVERSIBLE PROPERTIES AND CELL SHEET PRODUCTION METHOD USING SAME 有权
标题翻译：显示可逆性的温度响应表和使用相同的细胞片生产方法
公开(公告)号：US20130130384A1
公开(公告)日：2013-05-23
申请号：US13703318
申请日：2011-06-09
申请人： Kouji Okamoto , Erika Yoshino
发明人： Kouji Okamoto , Erika Yoshino
IPC分类号： C12N5/00
CPC分类号： C12N5/0068 , A61L27/227 , C07K14/78 , C12M23/20 , C12M25/14 , C12M33/00 , C12N2533/50 , C12N2539/10
摘要： A temperature responsive sheet is disclosed that comprises a chemically modified water-soluble elastin obtained by N-acylating at least some of the primary amines and secondary amines contained in a high molecular weight water-soluble elastin molecule and coupling some or all of carboxyl groups contained in the molecule with a glycine alkyl ester. Also is disclosed a process for producing a cell sheet that comprises preparing above the temperature responsive sheet a film that functions as a scaffold for animal cells, culturing specific cells on the film so as to prepare a cell sheet, and subsequently separating the cell sheet and the temperature responsive sheet comprising the chemically modified water-soluble elastin under conditions of no greater than the culturing temperature for the cells.
摘要翻译：公开了一种温度响应性片材，其包含通过将包含在高分子量水溶性弹性蛋白分子中的至少一些伯胺和仲胺进行N-酰化获得的化学改性的水溶性弹性蛋白，并将所含羧基的一些或全部偶联在具有甘氨酸烷基酯的分子中。还公开了一种制备细胞片的方法，其包括在温度响应片以上制备用作动物细胞支架的膜，在膜上培养特定细胞以制备细胞片，然后分离细胞片和在不高于细胞的培养温度的条件下，温度响应片材包含化学改性的水溶性弹性蛋白。

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