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21. 发明授权

US07521358B2 Process integration scheme to lower overall dielectric constant in BEoL interconnect structures 有权
标题翻译：过程集成方案，以降低BEoL互连结构中的总体介电常数
公开(公告)号：US07521358B2
公开(公告)日：2009-04-21
申请号：US11732198
申请日：2007-04-02
申请人： Nicolas Bright , Dave Hemker , Fritz C. Redeker , Yezdi Dordi
发明人： Nicolas Bright , Dave Hemker , Fritz C. Redeker , Yezdi Dordi
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76822 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.
摘要翻译：提供了后端（BEoL）互连结构及其制造方法。这些结构的特征在于导线越窄，总介电常数值越小。保形扩散阻挡层和选择性形成的覆盖层用于将导线和通孔与互连结构中的周围电介质层隔离。本发明的方法采用技术来缩小光致抗蚀剂掩模中的开口，以便限定更窄的通孔。更窄的通孔增加了通孔和导电线之间可以容许的不对准量。

22. 发明申请

US20080188970A1 Methods and Arrangement for Creating Recipes Using Best-Known Methods 有权
标题翻译：使用最佳方法制作食谱的方法和安排
公开(公告)号：US20080188970A1
公开(公告)日：2008-08-07
申请号：US11536582
申请日：2006-09-28
申请人： Chung-Ho Huang , Shih-Jeun Fan , Chin Chuan Chang , Nicolas Bright
发明人： Chung-Ho Huang , Shih-Jeun Fan , Chin Chuan Chang , Nicolas Bright
IPC分类号： G06F19/00
CPC分类号： G06N5/022 , G05B2219/32097 , G05B2219/45031
摘要： A method for affecting a creation of a recipe for processing a substrate in a processing system is provided. The method includes providing a best-know method driven recipe editor. The best-known method driven recipe editor incorporates best-known methods (BKMs), which are best practice specifications for the recipe. The method also includes creating a plurality of BKM modules based on the BKMs for the recipe. The method further includes defining rules for parameters in the plurality of BKM modules. The rules are propagated by the BKMs. The methods moreover includes creating a BKM driven recipe by employing the best-known method driven recipe editor to enter values for the parameters within the guidelines of BKM rules.
摘要翻译：提供了一种用于影响在处理系统中处理衬底的配方的创建的方法。该方法包括提供最知名的方法驱动的食谱编辑器。最着名的方法驱动的食谱编辑器包含最着名的方法（BKM），这是方法的最佳实践规范。该方法还包括基于用于配方的BKM创建多个BKM模块。该方法还包括为多个BKM模块中的参数定义规则。规则由BKM传播。方法还包括通过采用最着名的方法驱动的配方编辑器来创建BKM驱动的配方，以便在BKM规则的指导下输入参数的值。

23. 发明申请

US20060257750A1 Reticle alignment and overlay for multiple reticle process 有权
标题翻译：掩模版校准和覆盖多个标线工艺
公开(公告)号：US20060257750A1
公开(公告)日：2006-11-16
申请号：US11126466
申请日：2005-05-10
申请人： S.M. Sadjadi , Nicolas Bright
发明人： S.M. Sadjadi , Nicolas Bright
IPC分类号： G03F1/00 , G03F9/00 , G03C5/00
CPC分类号： H01L21/0338 , G03F7/70433 , G03F7/70466
摘要： A method for generating a plurality of reticle layouts is provided. A feature layout with a feature layout pitch is received. A plurality of reticle layouts is generated from the feature layout where each reticle layout of the plurality of reticle layouts has a reticle layout pitch and where each reticle layout pitch is at least twice the feature layout pitch.
摘要翻译：提供了一种用于产生多个标线布局的方法。接收具有特征布局间距的特征布局。从特征布局生成多个标线布局，其中多个标线布局的每个标线布局具有标线布局间距，并且其中每个标线布局间距至少是特征布局间距的两倍。

24. 发明申请

US20060166485A1 Methods for making dual-damascene dielectric structures 有权
公开(公告)号：US20060166485A1
公开(公告)日：2006-07-27
申请号：US11389428
申请日：2006-03-23
申请人： Jay Uglow , Nicolas Bright , Dave Hemker , Kenneth MacWilliams , Jeffrey Benzing , Timothy Archer
发明人： Jay Uglow , Nicolas Bright , Dave Hemker , Kenneth MacWilliams , Jeffrey Benzing , Timothy Archer
IPC分类号： H01L21/4763
CPC分类号： H01L21/76835 , H01L21/02126 , H01L21/02164 , H01L21/022 , H01L21/02304 , H01L21/31116 , H01L21/314 , H01L21/31633 , H01L21/76807 , H01L21/76822
摘要： A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry. The etching is timed to etch through a partial thickness of the low dielectric constant layer and the first etch chemistry is optimized to a selected low dielectric constant material. The method further includes forming a via hole in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In a specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

25. 发明授权

US07029368B2 Apparatus for controlling wafer temperature in chemical mechanical polishing 失效
标题翻译：用于控制化学机械抛光中晶片温度的装置
公开(公告)号：US07029368B2
公开(公告)日：2006-04-18
申请号：US10722729
申请日：2003-11-25
申请人： Nicolas Bright , David J. Hemker
发明人： Nicolas Bright , David J. Hemker
IPC分类号： B24B1/00
CPC分类号： B24B37/015 , B24B37/30
摘要： Apparatus controls the temperature of a wafer for chemical mechanical polishing operations. A wafer carrier wafer mounting surface positions a wafer adjacent to a thermal energy transfer unit for transferring energy relative to the wafer. A thermal energy detector oriented adjacent to the wafer mounting surface detects the temperature of the wafer. A controller is responsive to the detector for controlling the supply of thermal energy relative to the thermal energy transfer unit. Embodiments include defining separate areas of the wafer, providing separate sections of the thermal energy transfer unit for each separate area, and separately detecting the temperature of each separate area to separately control the supply of thermal energy relative to the thermal energy transfer unit associated with the separate area.
摘要翻译：设备控制用于化学机械抛光操作的晶片的温度。晶片载体晶片安装表面将晶片邻近热能传递单元定位，以相对于晶片转移能量。定位成与晶片安装表面相邻的热能检测器检测晶片的温度。控制器响应于检测器来控制相对于热能传递单元的热能供应。实施例包括限定晶片的分开的区域，为每个单独的区域提供热能传递单元的分开的部分，并且单独地检测每个分离区域的温度，以单独地控制相对于与所述热能传递单元相关联的热能传递单元的热能供应分开区域。

26. 发明授权

US06736720B2 Apparatus and methods for controlling wafer temperature in chemical mechanical polishing 有权
标题翻译：用于控制化学机械抛光中晶片温度的装置和方法
公开(公告)号：US06736720B2
公开(公告)日：2004-05-18
申请号：US10033455
申请日：2001-12-26
申请人： Nicolas Bright , David J. Hemker
发明人： Nicolas Bright , David J. Hemker
IPC分类号： B24B100
CPC分类号： B24B37/015 , B24B37/30
摘要： Apparatus and methods control the temperature of a wafer for chemical mechanical polishing operations. A wafer carrier has a wafer mounting surface for positioning the wafer adjacent to a thermal energy transfer unit for transferring energy relative to the wafer. A thermal energy detector is oriented adjacent to the wafer mounting surface for detecting the temperature of the wafer. A controller is responsive to the detector for controlling the supply of thermal energy relative to the thermal energy transfer unit. Embodiments include defining separate areas of the wafer, providing separate sections of the thermal energy transfer unit for each separate area, and separately detecting the temperature of each separate area to separately control the supply of thermal energy relative to the thermal energy transfer unit associated with the separate area.
摘要翻译：设备和方法控制用于化学机械抛光操作的晶片的温度。晶片载体具有用于将晶片定位在与热能传递单元相邻的晶片安装表面，用于相对于晶片转移能量。热能检测器定位成与晶片安装表面相邻，用于检测晶片的温度。控制器响应于检测器来控制相对于热能传递单元的热能供应。实施例包括限定晶片的分开的区域，为每个单独的区域提供热能传递单元的分开的部分，并且单独地检测每个分离区域的温度，以单独地控制相对于与所述热能传递单元相关联的热能传递单元的热能供应分开区域。

27. 发明授权

US06194325B1 Oxide etch process with high selectivity to nitride suitable for use on surfaces of uneven topography 失效
标题翻译：氧化物蚀刻工艺，对氮化物具有高选择性，适用于不均匀地形的表面
公开(公告)号：US06194325B1
公开(公告)日：2001-02-27
申请号：US08552030
申请日：1995-12-04
申请人： Chan Lon Yang , Jeffrey Marks , Nicolas Bright , Kenneth S. Collins , David Groechel , Peter Keswick
发明人： Chan Lon Yang , Jeffrey Marks , Nicolas Bright , Kenneth S. Collins , David Groechel , Peter Keswick
IPC分类号： H01L21302
CPC分类号： H01J37/32871 , H01J37/321 , H01L21/31116
摘要： A plasma etch process is described for the etching of oxide with a high selectivity to nitride, including nitride formed on uneven surfaces of a substrate, e.g., on sidewalls of steps on an integrated circuit structure. The addition of one or more hydrogen-containing gases, preferably one or more hydrofluorocarbon gases, to one or more fluorine-substituted hydrocarbon etch gases and a scavenger for fluorine, in a plasma etch process for etching oxide in preference to nitride, results in a high selectivity to nitride which is preserved regardless of the topography of the nitride portions of the substrate surface. In a preferred embodiment, one or more oxygen-bearing gases are also added to reduce the overall rate of polymer deposition on the chamber surfaces and on the surfaces to be etched, which can otherwise reduce the etch rate and cause excessive polymer deposition on the chamber surfaces. The fluorine scavenger is preferably an electrically grounded silicon electrode associated with the plasma.
摘要翻译：描述了用于蚀刻具有对氮化物的高选择性的氧化物的等离子体蚀刻工艺，包括在衬底的不平坦表面上形成的氮化物，例如在集成电路结构上的台阶侧壁上。在优先于氮化物蚀刻氧化物的等离子体蚀刻工艺中，向一种或多种氟取代烃蚀刻气体和氟清除剂中加入一种或多种含氢气体，优选一种或多种氢氟烃气体，导致对氮化物的高选择性，与衬底表面的氮化物部分的形貌无关地被保留。在一个优选的实施方案中，还加入一种或多种含氧气体以降低腔室表面和待蚀刻表面上的聚合物沉积的总体速率，否则可降低蚀刻速率并导致室上过量的聚合物沉积表面。氟清除剂优选为与等离子体相关联的电接地硅电极。

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