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1. 发明授权

US07521358B2 Process integration scheme to lower overall dielectric constant in BEoL interconnect structures 有权
标题翻译：过程集成方案，以降低BEoL互连结构中的总体介电常数
公开(公告)号：US07521358B2
公开(公告)日：2009-04-21
申请号：US11732198
申请日：2007-04-02
申请人： Nicolas Bright , Dave Hemker , Fritz C. Redeker , Yezdi Dordi
发明人： Nicolas Bright , Dave Hemker , Fritz C. Redeker , Yezdi Dordi
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76822 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.
摘要翻译：提供了后端（BEoL）互连结构及其制造方法。这些结构的特征在于导线越窄，总介电常数值越小。保形扩散阻挡层和选择性形成的覆盖层用于将导线和通孔与互连结构中的周围电介质层隔离。本发明的方法采用技术来缩小光致抗蚀剂掩模中的开口，以便限定更窄的通孔。更窄的通孔增加了通孔和导电线之间可以容许的不对准量。

2. 发明授权

US07128803B2 Integration of sensor based metrology into semiconductor processing tools 失效
标题翻译：将基于传感器的计量学整合到半导体处理工具中
公开(公告)号：US07128803B2
公开(公告)日：2006-10-31
申请号：US10186472
申请日：2002-06-28
申请人： Aleksander Owczarz , Yehiel Gotkis , Dave Hemker , Rodney Kistler
发明人： Aleksander Owczarz , Yehiel Gotkis , Dave Hemker , Rodney Kistler
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： B24B1/005 , B24B37/013 , B24B49/105 , B24B57/02 , H01L21/67253
摘要： A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A cluster of sensors external to the CMP tool is included. The cluster of sensors is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The cluster of sensors provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.
摘要翻译：提供了一种用于处理晶片的系统。该系统包括化学机械平面化（CMP）工具。 CMP工具包括限定在壳体内的晶片载体。载体膜固定到底表面并支撑晶片。嵌入晶片载体的传感器。传感器被配置为在晶片中感应涡流以确定晶片的接近度和厚度。包括CMP工具外部的一组传感器。传感器组与嵌入晶片载体中的传感器进行通信，并且基本上消除了距离灵敏度。传感器簇提供晶片的初始厚度，以允许对嵌入在晶片载体中的传感器执行校准。校准偏移了在CMP操作期间确定晶片厚度的不准确性的变量。还提供了一种方法和装置。

3. 发明申请

US20060166485A1 Methods for making dual-damascene dielectric structures 有权
公开(公告)号：US20060166485A1
公开(公告)日：2006-07-27
申请号：US11389428
申请日：2006-03-23
申请人： Jay Uglow , Nicolas Bright , Dave Hemker , Kenneth MacWilliams , Jeffrey Benzing , Timothy Archer
发明人： Jay Uglow , Nicolas Bright , Dave Hemker , Kenneth MacWilliams , Jeffrey Benzing , Timothy Archer
IPC分类号： H01L21/4763
CPC分类号： H01L21/76835 , H01L21/02126 , H01L21/02164 , H01L21/022 , H01L21/02304 , H01L21/31116 , H01L21/314 , H01L21/31633 , H01L21/76807 , H01L21/76822
摘要： A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry. The etching is timed to etch through a partial thickness of the low dielectric constant layer and the first etch chemistry is optimized to a selected low dielectric constant material. The method further includes forming a via hole in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In a specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

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