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21. 发明授权

US07379517B1 Method and apparatus for signaling characteristics of a transmitted signal 有权
标题翻译：用于发送信号的特征的方法和装置
公开(公告)号：US07379517B1
公开(公告)日：2008-05-27
申请号：US10444913
申请日：2003-05-23
申请人： William C. Black
发明人： William C. Black
IPC分类号： H04L7/00 , H04L7/06
CPC分类号： H04L7/04 , H04L5/20 , H04L7/043
摘要： A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal (MODE) represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters (300 and 400) and is detected using differential receiver (600). One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.
摘要翻译：提供了一种允许利用差分传输网络的共模特性以提供附加数据信号的方法和装置。信号（MODE）表示二进制信号或多值信号，以允许一个或多个信息位的信令。通过发射机（300和400）中的共模电压的变化发生信令，并使用差分接收机（600）进行检测。呈现一个实施例，其实现扩展游程长度数据序列的信令，以允许在序列的整个传输过程中继续的发射机/接收机同步。在替代实施例中，当共模信令路径不可用时，提供单独的数据路径来用信号通知延长的游程长度序列。

22. 发明授权

US07376205B1 Device and method for compensation of transmission line distortion 有权
标题翻译：传输线失真补偿的装置和方法
公开(公告)号：US07376205B1
公开(公告)日：2008-05-20
申请号：US09989937
申请日：2001-11-20
申请人： William C. Black
发明人： William C. Black
IPC分类号： H04L25/03 , H04L25/06 , H04L25/10 , H04L27/08
CPC分类号： H04L25/0288 , H04L25/03878
摘要： A system, device, and method for compensation of distortion caused by transmission line effects are disclosed herein. An output port including a feed-forward circuit parallel to the output impedance of an output driver compensates for distortion introduced by transmitting data over a transmission medium. The compensated output driver is utilized to transmit data between devices or circuits connected using conductive traces on printed circuit boards.
摘要翻译：本文公开了用于补偿由传输线效应引起的失真的系统，装置和方法。包括与输出驱动器的输出阻抗平行的前馈电路的输出端口补偿通过传输介质发送数据而引入的失真。补偿输出驱动器用于在使用印刷电路板上的导电迹线连接的设备或电路之间传输数据。

23. 发明授权

US07227375B2 DAC based driver with selectable pre-emphasis signal levels 有权
标题翻译：基于DAC的驱动器，具有可选的预加重信号电平
公开(公告)号：US07227375B2
公开(公告)日：2007-06-05
申请号：US11218962
申请日：2005-09-01
申请人： Eric D. Groen , Charles W. Boecker , William C. Black
发明人： Eric D. Groen , Charles W. Boecker , William C. Black
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H04L25/0282 , H04L25/028 , H04L25/0292
摘要： A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added to the primary current level produced by the primary current driver. The pre-emphasis current has either negative or positive magnitude based upon a pre-emphasis signal logic state. A first current selection module defines a reference signal that is used to select the primary current driver output signal magnitude in a first current mirror, while a second current selection module is used to define a second reference signal that selects a pre-emphasis current driver signal magnitude in a second current mirror. Logic generates a binary signal to both the first and second current selection modules to select the current levels as well as the pre-emphasis signal.
摘要翻译：具有可选择的预加重和驱动器信号幅度的发射线路驱动器包括用于设置初级电流电平的初级电流驱动器和预加重电流驱动器，其提供与产生的初级电流电平重叠或相加的额外量的电流由主要的当前驱动程序。基于预加重信号逻辑状态，预加重电流具有负幅度或正幅度。第一当前选择模块定义用于在第一电流镜中选择初级电流驱动器输出信号幅度的参考信号，而第二电流选择模块用于定义选择预加重电流驱动器信号的第二参考信号在第二电流镜中的大小。逻辑生成二进制信号到第一和第二电流选择模块以选择当前电平以及预加重信号。

24. 发明授权

US07196545B1 High frequency latch 有权
标题翻译：高频锁存
公开(公告)号：US07196545B1
公开(公告)日：2007-03-27
申请号：US10812549
申请日：2004-03-29
申请人： Eric D. Groen , Charles W. Boecker , William C. Black
发明人： Eric D. Groen , Charles W. Boecker , William C. Black
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K3/012 , H03K3/356 , H03K19/1778
摘要： A high frequency latch comprising a latch and a plurality of buffers coupled to peak load circuitry produces a peak response at a desired frequency of operation as well as isolating each high frequency latch output of a plurality of outputs to substantially reduce the effects of a kickback signal coupled into the latch output. The peaked load circuitry comprises selectable resistive elements and selectable capacitive elements coupled as a high pass filter to change the bias on a saturation region MOSFET configured as an active load. The high pass filter produces positive feedback on the saturation region MOSFET to increase the bias at high frequencies thereby producing an increased response at a desired operating frequency.
摘要翻译：包括锁存器和耦合到峰值负载电路的多个缓冲器的高频锁存器在期望的操作频率处产生峰值响应，并且隔离多个输出端的每个高频锁存器输出以显着减少反冲信号的影响耦合到锁存器输出。峰值负载电路包括可选择的电阻元件和作为高通滤波器耦合的可选择的电容元件，以改变被配置为有源负载的饱和区域MOSFET上的偏置。高通滤波器在饱和区域MOSFET上产生正反馈以增加高频处的偏置，从而在期望的工作频率下产生增加的响应。

25. 发明授权

US07188283B1 Communication signal testing with a programmable logic device 有权
标题翻译：通信信号测试与可编程逻辑器件
公开(公告)号：US07188283B1
公开(公告)日：2007-03-06
申请号：US10660243
申请日：2003-09-11
申请人： Matthew S. Shafer , Bodhisattva Das , William C. Black , Scott A. Irwin
发明人： Matthew S. Shafer , Bodhisattva Das , William C. Black , Scott A. Irwin
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31715 , G06F11/221 , H04L43/50
摘要： Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.
摘要翻译：描述了用于配置可编程逻辑器件以在信号通道上执行测试的方法和装置。可编程逻辑器件的可配置逻辑被配置为测试模式。可配置互连被配置用于从或从可配置逻辑传送到耦合到可配置输入/输出互连的收发器以从其传送测试信号。

26. 发明授权

US06975132B2 DAC based driver with selectable pre-emphasis signal levels 有权
标题翻译：基于DAC的驱动器，具有可选的预加重信号电平
公开(公告)号：US06975132B2
公开(公告)日：2005-12-13
申请号：US10660062
申请日：2003-09-11
申请人： Eric D. Groen , Charles W. Boecker , William C. Black
发明人： Eric D. Groen , Charles W. Boecker , William C. Black
IPC分类号： H04L25/02 , H04L25/52 , H03K19/003 , H03K19/0175
CPC分类号： H04L25/0282 , H04L25/028 , H04L25/0292
摘要： A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added to the primary current level produced by the primary current driver. The pre-emphasis current has either negative or positive magnitude based upon a pre-emphasis signal logic state. A first current selection module defines a reference signal that is used to select the primary current driver output signal magnitude in a first current mirror, while a second current selection module is used to define a second reference signal that selects a pre-emphasis current driver signal magnitude in a second current mirror. Logic generates a binary signal to both the first and second current selection modules to select the current levels as well as the pre-emphasis signal.
摘要翻译：具有可选择的预加重和驱动器信号幅度的发射线路驱动器包括用于设置初级电流电平的初级电流驱动器和预加重电流驱动器，其提供与产生的初级电流电平重叠或相加的额外量的电流由主要的当前驱动程序。基于预加重信号逻辑状态，预加重电流具有负幅度或正幅度。第一当前选择模块定义用于在第一电流镜中选择初级电流驱动器输出信号幅度的参考信号，而第二电流选择模块用于定义选择预加重电流驱动器信号的第二参考信号在第二电流镜中的大小。逻辑生成二进制信号到第一和第二电流选择模块以选择当前电平以及预加重信号。

27. 发明授权

US06768356B1 Apparatus for and method of implementing time-interleaved architecture 失效
标题翻译：实现时间交织架构的装置和方法
公开(公告)号：US06768356B1
公开(公告)日：2004-07-27
申请号：US09656763
申请日：2000-09-07
申请人： Lin Wu , William C. Black
发明人： Lin Wu , William C. Black
IPC分类号： H03L706
CPC分类号： H03L7/081 , H03K5/133 , H03K2005/00026 , H03L7/0812
摘要： In accordance with a preferred embodiment, a time-interleaved (or multi-phase) architecture is provided having individual control of a plurality of output signals or phases. The time-interleaved architecture may be implemented using a first set of delay cells such as those in a ring oscillator or a delay line device receiving overall control of its output signals by a global control signal. The global control signal may be issued by a phase-locked loop, delay-locked loop, or other like structure. A second set of delay cells is provided to further delay the output signals produced by the first set of delay cells. The second set of delay cells are controlled by individual control signals uniquely calibrated in accordance with a preferred embodiment of the invention to provide uniform (or substantially) uniform time spacing between output signals.
摘要翻译：根据优选实施例，提供具有多个输出信号或相位的单独控制的时间交织（或多相）架构。可以使用第一组延迟单元来实现时间交织体系结构，例如环形振荡器或延迟线设备中的延迟单元，其通过全局控制信号接收对其输出信号的总体控制。全局控制信号可以由锁相环，延迟锁定环或其它类似结构发出。提供第二组延迟单元以进一步延迟由第一组延迟单元产生的输出信号。第二组延迟单元由根据本发明的优选实施例唯一校准的单独控制信号来控制，以在输出信号之间提供均匀（或基本上）均匀的时间间隔。

28. 发明授权

US06542000B1 Nonvolatile programmable logic devices 失效
标题翻译：非易失性可编程逻辑器件
公开(公告)号：US06542000B1
公开(公告)日：2003-04-01
申请号：US09627576
申请日：2000-07-28
申请人： William C. Black , Bodhisattva Das , Marwan M. Hassoun , Edward K. F. Lee
发明人： William C. Black , Bodhisattva Das , Marwan M. Hassoun , Edward K. F. Lee
IPC分类号： H03K738
CPC分类号： G11C14/00 , H03K3/356008 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/1778
摘要： In this invention, three schemes of nonvolatile FPLD structures are proposed using a latch that has been disclosed herein. In the first proposed scheme the latches, which can be designed using either GMR or SDT devices, will work as interconnects in a conventional Programmable Logic Array (PLA). In the second proposed scheme, the latches will constitute the look-up table for a standard PLA. In the third proposed scheme, the latch itself will work as a nonvolatile Programmable Logic Device (PLD) structure. This FPLD latch will have 2n GMR or SDT resistors, instead of just 2, for an n-input logic gate. By programming the resistors differently, in each scheme, numerous different logic functions from the same logic gate can be achieved.
摘要翻译：在本发明中，使用本文公开的锁存器来提出三种非易失FPLD结构方案。在第一个提出的方案中，可以使用GMR或SDT器件设计的锁存器将在传统的可编程逻辑阵列（PLA）中用作互连。在第二个提出的方案中，锁存器将构成标准PLA的查找表。在第三个提出的方案中，锁存器本身将用作非易失性可编程逻辑器件（PLD）结构。对于n输入逻辑门，该FPLD锁存器将具有2n GMR或SDT电阻，而不仅仅是2。通过对电阻器编程不同，在每个方案中，可以实现来自相同逻辑门的许多不同的逻辑功能。

29. 发明授权

US06317359B1 Non-volatile magnetic circuit 失效
标题翻译：非易失性磁路
公开(公告)号：US06317359B1
公开(公告)日：2001-11-13
申请号：US09605113
申请日：2000-06-28
申请人： William C. Black , Marwan M. Hassoun
发明人： William C. Black , Marwan M. Hassoun
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A device and method for sensing the status of a non-volatile magnetic latch. A cross-coupled inverter pair latch cell is employed for the data sensing. During the ‘Sense’ cycles, the inputs to the latch cell are from Giant Magneto-Resistive effect devices, each located in its respective inverter pair. The magneto-resistive storage devices have complimentary resistance states written into them. A switch, connected to the inverter pairs, is used to reset and initiate a regenerative sequence. Whenever the switch is turned on (reset) and off (regenerate), the latch cell will sense a potential imbalance generated by the magneto-resistive storage devices with complimentary resistance. During regeneration, the imbalance will be amplified and eventually the inverter pairs will reach a logic high or logic low state. The latch can be used as a memory circuit, however, upon loss of power the memory is retained. The state of the circuit is retained inside of GMR components. On-chip current lines are used to control the states of the components.
摘要翻译：一种用于感测非易失性磁性锁存器的状态的装置和方法。采用交叉耦合的反相器锁存单元进行数据检测。在“感应”周期中，锁存单元的输入来自巨磁电阻效应器件，每个位于其相应的反相器对中，磁阻存储器件具有写入的互补电阻状态，逆变器对，用于复位和启动再生序列，每当开关打开（复位）和关闭（再生）时，锁存单元将感测由具有互补电阻的磁阻存储器件产生的潜在不平衡，在再生期间，不平衡将被放大，最终逆变器对将达到逻辑高电平或逻辑低电平状态，锁存器可用作存储电路，但在存储器保持失电时，电路的状态保持在的GMR组件，片上电流线用于控制组件的状态。

30. 发明授权

US09391669B2 Communication using multiple conductor cable 有权
标题翻译：使用多芯电缆进行通讯
公开(公告)号：US09391669B2
公开(公告)日：2016-07-12
申请号：US13935186
申请日：2013-07-03
申请人： William C. Black
发明人： William C. Black
IPC分类号： H04B3/56 , H04B3/50 , H04B1/707 , H04B3/54
CPC分类号： H04B3/56 , H04B1/707 , H04B3/50 , H04B3/54 , H04B2203/5458 , H04B2203/5466 , H04B2203/5475 , H04B2203/5483
摘要： A method of communication over a composite cable having a plurality of conductors, the method including placing an inductive coupler around the composite cable, coupling the composite cable to a signal input or output using the inductive coupler around the composite cable to communicate a signal to or from the composite cable, wherein the signal is communicated across the composite cable from a first location to a second location, wherein the inductive coupler is at one of the first location and the second location.
摘要翻译：一种通过具有多个导体的复合电缆进行通信的方法，所述方法包括将电感耦合器放置在复合电缆周围，将复合电缆耦合到信号输入或输出端，使用电感耦合器围绕复合电缆将信号传送到或其中所述信号通过所述复合电缆从第一位置传递到第二位置，其中所述电感耦合器处于所述第一位置和所述第二位置之一。

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