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21. 发明申请

US20050285188A1 LDMOS transistor 有权
标题翻译： LDMOS晶体管
公开(公告)号：US20050285188A1
公开(公告)日：2005-12-29
申请号：US10875105
申请日：2004-06-23
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L29/06 , H01L29/47 , H01L29/76 , H01L29/78
CPC分类号： H01L29/782 , H01L27/0727 , H01L29/0619 , H01L29/0653 , H01L29/47 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.
摘要翻译： LDMOS晶体管具有插入在LDMOS晶体管的掺杂区域的中心处的肖特基二极管。典型的LDMOS晶体管在中心具有漂移区域。在这种情况下，肖特基二极管插在该漂移区的中心，其具有提供从正向连接到源极到漏极的肖特基二极管的作用，使得漏极电压被钳位到低于PN结的电压阈值，从而避免正向偏置PN结。一种替代方案是将肖特基二极管插入其中形成源的阱，其位于LDMOS晶体管的外围。在这种情况下，肖特基二极管的形成方式不同，但仍然在正向方向上从源极到漏极连接，以在漏极处实现所需的电压钳位。

22. 发明申请

US20050275055A1 Schottky device 失效
标题翻译：肖特基装置
公开(公告)号：US20050275055A1
公开(公告)日：2005-12-15
申请号：US10856602
申请日：2004-05-28
申请人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose
发明人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/06 , H01L27/07 , H03K19/00
CPC分类号： H01L27/0727 , H01L27/0629
摘要： A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.
摘要翻译：正交肖特基二极管或具有肖特基二极管特性和MOS晶体管的器件串联耦合以提供泄漏电流和击穿电压的显着改进，只有正向电流的降低很小。在反向偏置情况下，存在小的反向偏置电流，但由于MOS晶体管，肖特基二极管两端的电压保持较小。几乎所有的反向偏置电压都跨越MOS晶体管，直到MOS晶体管故障。然而，该晶体管击穿不是最初的破坏性，因为肖特基二极管限制了电流。随着反向偏压持续增加，肖特基二极管开始吸收更多的电压。这增加了漏电流，但是在晶体管和肖特基二极管之间的击穿电压稍微相加。

23. 发明授权

US06815780B1 Semiconductor component with substrate injection protection structure 有权
标题翻译：半导体元件具有基板注入保护结构
公开(公告)号：US06815780B1
公开(公告)日：2004-11-09
申请号：US10417972
申请日：2003-04-15
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L2976
CPC分类号： H01L21/76224 , H01L21/763
摘要： A semiconductor component includes a semiconductor substrate (210) having a first conductivity type, a semiconductor epitaxial layer (220) having the first conductivity type located over the semiconductor substrate, a first semiconductor device (110) and a second semiconductor device (130) located in the semiconductor epitaxial layer and including, respectively, a first semiconductor region (120) and a second semiconductor region (140), both having the second conductivity type, an ohmic contact region (150) in the semiconductor epitaxial layer having the first conductivity type and located between the first and second semiconductor devices, and at least one electrically insulating trench (160, 360) located in the semiconductor epitaxial layer and circumscribing at least the first semiconductor device. The semiconductor epitaxial layer has a doping concentration lower than a doping concentration of the semiconductor substrate.

24. 发明授权

US06734524B1 Electronic component and method of manufacturing same 有权
标题翻译：电子元件及其制造方法
公开(公告)号：US06734524B1
公开(公告)日：2004-05-11
申请号：US10335030
申请日：2002-12-31
申请人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui
发明人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui
IPC分类号： H01L2900
CPC分类号： H01L27/088 , H01L21/76232
摘要： An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.
摘要翻译：电子部件包括半导体衬底（110），半导体衬底上的外延半导体层（120,221,222）以及外延半导体层中的半导体区域（130,230）。外延半导体层具有上表面（123）。外延半导体层的第一部分（121）位于半导体区域的下方，并且外延半导体层的第二部分（122）位于半导体区域的上方。半导体衬底和外延半导体层的第一部分具有第一导电类型，并且半导体区域具有第二导电类型。至少一个电绝缘沟槽（140,240）从外延半导体层的上表面延伸到半导体区域的至少一部分。半导体衬底的掺杂浓度高于外延半导体层的第一部分的掺杂浓度。

25. 发明授权

US10376179B2 MPR slice selection for visualization of catheter in three-dimensional ultrasound 有权
公开(公告)号：US10376179B2
公开(公告)日：2019-08-13
申请号：US14113035
申请日：2012-04-19
申请人： Vijay Parthasarathy , Ameet Kumar Jain , Charles Ray Hatt, III , Amish N. Raval
发明人： Vijay Parthasarathy , Ameet Kumar Jain , Charles Ray Hatt, III , Amish N. Raval
IPC分类号： A61B5/05 , A61B5/06 , A61B8/08 , A61B6/12 , A61B6/00 , A61B8/00 , G06T15/08 , A61M25/01 , A61B34/20 , A61B17/00 , A61B90/00
摘要： A system employs an interventional tool (30), ultrasound imaging system and a multi-planar reformatting module (40). The interventional tool (30) has one or more image tracking points (31). The ultrasound imaging system includes an ultrasound probe (20) operable for generating an ultrasound volume image (22) of a portion or an entirety of the interventional tool (30) within an anatomical region. The multi-planar reformatting imaging module (40) generates two or more multi- planar reformatting images (41) of the interventional tool (30) within the anatomical region. A generation of the two multi-planar reformatting images (41) includes an identification of each image tracking point (31) within the ultrasound volume image (22), and a utilization of each identified image tracking point (31) as an origin of the multi-planar reformatting images (41).

26. 发明授权

US09993304B2 Visualization of catheter of three-dimensional ultrasound 有权
公开(公告)号：US09993304B2
公开(公告)日：2018-06-12
申请号：US13997800
申请日：2012-01-10
申请人： Pingkun Yan , Vijay Parthasarathy , Robert Manzke , Ameet Kumar Jain
发明人： Pingkun Yan , Vijay Parthasarathy , Robert Manzke , Ameet Kumar Jain
IPC分类号： A61B34/20 , A61B6/12 , A61B8/08 , A61B8/00
CPC分类号： A61B34/20 , A61B6/12 , A61B8/0883 , A61B8/466 , A61B8/483
摘要： An image-guided system includes an X-ray imaging device for generating one or more X-ray images illustrating a tool within an anatomical region, and an ultrasound imaging device for generating an ultrasound image illustrating the tool within the anatomical region. The image-guided system further includes a tool tracking device for visually tracking the tool within the anatomical region. In operation, the tool tracking device localizes a portion of the tool as located within the ultrasound image responsive to an identification of the portion of the tool as located within the X-ray image(s), and executes an image segmentation of an entirety of the tool as located within the ultrasound image relative to a localization of the portion of the tool as located within the ultrasound image.

27. 发明授权

US08653600B2 High-voltage monolithic schottky device structure 有权
标题翻译：高压单片肖特基器件结构
公开(公告)号：US08653600B2
公开(公告)日：2014-02-18
申请号：US13487025
申请日：2012-06-01
申请人： Vijay Parthasarathy
发明人： Vijay Parthasarathy
IPC分类号： H01L29/66
CPC分类号： H01L29/8725 , H01L29/0619 , H01L29/0692 , H01L29/36 , H01L29/407
摘要： A semiconductor device includes a pillar formed on a substrate of the same conductivity type. The pillar has a vertical thickness that extends from a top surface down to the substrate. The pillar extends in first and second lateral directions in a loop shape. First and second dielectric regions are disposed on opposite lateral sides of the pillar, respectively. First and second conductive field plates are respectively disposed in the first and second dielectric regions. A metal layer is disposed on the top surface of the pillar, the metal layer forming a Schottky diode with respect to the pillar. When the substrate is raised to a high-voltage potential with respect to both the metal layer and the first and second field plates, the first and second field plates functioning capacitively to deplete the pillar of charge, thereby supporting the high-voltage potential along the vertical thickness of the pillar.
摘要翻译：半导体器件包括形成在相同导电类型的衬底上的柱。该柱具有从顶部表面向下延伸到基底的垂直厚度。支柱以第一和第二横向方向呈环形延伸。第一和第二电介质区域分别设置在柱的相对侧面上。第一和第二导电场板分别设置在第一和第二电介质区域中。金属层设置在柱的顶表面上，金属层相对于柱形成肖特基二极管。当基板相对于金属层和第一和第二场板两者升高到高压电位时，第一和第二场板电容地起作用以耗尽柱的电荷，从而支持沿着柱的垂直厚度。

28. 发明申请

US20120273885A1 High-Voltage Transistor Structure with Reduced Gate Capacitance 有权
标题翻译：具有降低栅极电容的高压晶体管结构
公开(公告)号：US20120273885A1
公开(公告)日：2012-11-01
申请号：US13532583
申请日：2012-06-25
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/0882 , H01L29/42368
摘要： In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.
摘要翻译：在一个实施例中，高电压场效应晶体管（HVFET）包括覆盖第一阱区的场氧化物层，所述场氧化物层具有第一厚度并且在第二横向方向上从漏极区延伸到接近第二阱地区。栅极氧化物覆盖沟道区域并且具有在第一横向方向上的第二尺寸。栅极在第二横向方向上从源极区域延伸到场氧化物层的一部分，栅极通过栅极氧化物与沟道区域绝缘，栅极在第一横向尺寸上延伸超过HVFET的非有效区域超过栅极氧化物的第二维度，栅极通过场氧化物层与无源区域上的第一和第二阱区绝缘。

29. 发明申请

US20120146105A1 High-voltage transistor device with integrated resistor 有权
标题翻译：具有集成电阻的高压晶体管器件
公开(公告)号：US20120146105A1
公开(公告)日：2012-06-14
申请号：US13385264
申请日：2012-02-10
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L27/06
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，在JFET的端子处提供的电压基本上与外部电压成比例的JFET。当外部电压大于夹断电压时，端子处提供的电压基本上恒定。当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。当外部电压为负时，电阻限制注入基板的电流。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。

30. 发明申请

US20120061755A1 Checkerboarded high-voltage vertical transistor layout 失效
标题翻译：棋盘式高压立式晶体管布局
公开(公告)号：US20120061755A1
公开(公告)日：2012-03-15
申请号：US13199792
申请日：2011-09-09
申请人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
发明人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
IPC分类号： H01L29/78
CPC分类号： H01L27/0211 , H01L27/0207 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。邻接第一和第二部分的晶体管段的外场板被分离或部分合并。

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