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21. 发明授权

US06255899B1 Method and apparatus for increasing interchip communications rates 失效
标题翻译：提高芯片间通信速率的方法和装置
公开(公告)号：US06255899B1
公开(公告)日：2001-07-03
申请号：US09388164
申请日：1999-09-01
申请人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2500
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/0652 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/16152 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： An assembly is provided that includes an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line extending directly through the interposer from the first surface to the second surface. A first IC is coupled to the first surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals thereto or for receiving such signals therefrom. A chip carrier having a cavity formed therein also may be provided wherein the second surface of the interposer is coupled to the chip carrier and the second IC is disposed within the cavity. One or more carrier signal lines may be provided within the chip carrier and coupled between the interposer and the second IC. The first and/or the second IC also may comprise control logic adapted to select a number of drivers within either IC that drive a particular signal line.
摘要翻译：提供了一种组件，其包括具有第一和第二基本上平坦的相对表面的插入件以及至少一个直线从第一表面延伸到第二表面的速度临界信号线。第一IC耦合到插入器的第一表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。第二IC耦合到插入器的第二表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。优选地，在插入器内提供至少一个非速度临界信号线，并且耦合到第一IC和/或第二IC的第二外部连接机构，用于向其递送非速度关键信号或用于从其接收这样的信号。还可以提供其中形成有空腔的芯片载体，其中插入器的第二表面耦合到芯片载体，并且第二IC设置在空腔内。可以在芯片载体内提供一个或多个载波信号线，并且耦合在插入器和第二IC之间。第一和/或第二IC还可以包括适于选择驱动特定信号线的IC内的多个驱动器的控制逻辑。

22. 发明授权

US06177818B1 Complementary depletion switch body stack off-chip driver 失效
标题翻译：互补耗尽开关体堆栈片外驱动
公开(公告)号：US06177818B1
公开(公告)日：2001-01-23
申请号：US09303508
申请日：1999-04-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , William R. Tonti
IPC分类号： H03B2100
CPC分类号： H03K19/09482 , H03K19/00361 , H03K19/018521
摘要： An off-chip driver circuit including an enhancement PFET, a depletion PFET, a depletion NFET and an enhancement NFET connected in series. The large enhancement PFET and large enhancement NFET turn off the OCD in tri-state and to turn off the unused half of the OCD to prevent overlap current when driving a ‘0’ or a ‘1’. A first gate signal is applied to the gate of the enhancement PFET and a second gate signal is applied to the enhancement NFET. A fixed voltage is connected to the gate of the depletion NFET and ground to gate of the depletion PFET. An output signal is obtained from a node between the depletion PFET and depletion NFET devices. In another embodiment, a reflection/overshoot sensor 60 is added. The output of sensor is connected to the body of a depletion PFET and an NFET. The feedback from sensor is such that the threshold voltage of the depletion devices are made more positive if the sensor detects that the output is being over-driven. A more positive threshold voltage will reduce the driver's IDS, but leaves the device in the linear mode.
摘要翻译：包括增强型PFET，耗尽型PFET，耗尽型NFET和增强型NFET的片外驱动电路。大增强型PFET和大增强型NFET在三态关闭OCD并关闭OCD的未使用的一半以防止在驱动“0”或“1”时重叠电流。第一栅极信号被施加到增强PFET的栅极，并且第二栅极信号被施加到增强NFET。固定电压连接到耗尽型NFET的栅极，并连接到耗尽PFET的栅极。从耗尽PFET和耗尽NFET器件之间的节点获得输出信号。在另一个实施例中，添加了反射/过冲传感器60。传感器的输出连接到耗尽PFET和NFET的主体。来自传感器的反馈使得如果传感器检测到输出被过驱动，则耗尽装置的阈值电压变得更为正。更正的阈值电压将减少驾驶员的IDS，但使设备处于线性模式。

23. 发明授权

US06369671B1 Voltage controlled transmission line with real-time adaptive control 有权
标题翻译：电压控制传输线具有实时自适应控制
公开(公告)号：US06369671B1
公开(公告)日：2002-04-09
申请号：US09281412
申请日：1999-03-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01P1185
CPC分类号： G11C7/12
摘要： A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.
摘要翻译：一种具有衬底的半导体结构，在衬底的一部分上方的绝缘体，绝缘体上方的导体; 以及在所述衬底的所述部分的相对侧上的所述衬底中的至少两个接触区域，其中所述接触区域之间的电压调制所述导体的电容。

24. 发明授权

US06177809B1 Redundant input/output driver circuit 失效
标题翻译：冗余输入/输出驱动电路
公开(公告)号：US06177809B1
公开(公告)日：2001-01-23
申请号：US09322470
申请日：1999-05-28
申请人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
发明人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
IPC分类号： H03K19094
CPC分类号： H03K19/00384 , H03K19/0005
摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.
摘要翻译：由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态状态的第一个片外驱动电路。

25. 发明授权

US06204140B1 Dynamic random access memory 有权
标题翻译：动态随机存取存储器
公开(公告)号：US06204140B1
公开(公告)日：2001-03-20
申请号：US09275337
申请日：1999-03-24
申请人： Ulrike Gruening , Jochen Beintner , Scott Halle , Jack A. Mandelman , Carl J. Radens , Juergen Wittmann , Jeffrey J. Welser
发明人： Ulrike Gruening , Jochen Beintner , Scott Halle , Jack A. Mandelman , Carl J. Radens , Juergen Wittmann , Jeffrey J. Welser
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10861
摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.
摘要翻译：一种方法包括在半导体本体中形成沟槽电容器。在电容器的上部形成凹部，该凹槽在半导体本体中具有侧壁。第一材料沉积在凹槽的侧壁和底部上方。第二种材料沉积在第一种材料上。在第二材料上提供面罩。掩模具有：掩蔽区域，以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹部底部的另一部分以暴露第二材料的下面部分。第二材料的暴露的下部部分的部分是选择性地去除，同时留下基本未蚀刻的暴露的第一材料的下部。选择性地去除半导体主体的第一材料和下部的暴露部分。隔离区形成在半导体本体的去除部分中。所述掩模设置在所述第二材料上方，具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域，以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分，第二材料的部分。在半导体本体的暴露的下部设置蚀刻，以在半导体本体中形成浅沟槽。在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。通过这种方法，允许更大的掩模不对准公差。

26. 发明授权

US06544837B1 SOI stacked DRAM logic 失效
标题翻译： SOI叠层DRAM逻辑
公开(公告)号：US06544837B1
公开(公告)日：2003-04-08
申请号：US09527743
申请日：2000-03-17
申请人： Ramachandra Divakauni , Mark C. Hakey , William H.-L. Ma , Jack A. Mandelman , William R. Tonti
发明人： Ramachandra Divakauni , Mark C. Hakey , William H.-L. Ma , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L2146
CPC分类号： H01L27/10867 , H01L22/32 , H01L23/481 , H01L23/535 , H01L27/10832 , H01L27/1203 , H01L2924/0002 , Y10S977/712 , Y10S977/721 , Y10S977/779 , Y10S977/90 , Y10S977/94 , H01L2924/00
摘要： A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.
摘要翻译：通过在晶片上粘合绝缘体层而形成的复合层状集成电路提供了诸如沟槽电容器DRAM阵列和高性能，低功率，低电压绝缘体上硅（SOI）开关晶体管和短信号传播路径之类的不相容技术的组合在形成在芯片的各个晶片层上的器件之间。在优选实施例中，通过在集成电路器件上的晶片亲水键合然后使用注入的氢和低温热处理将第二晶片的层切割掉，形成SOI晶片。各种结构和组合物的其它晶片可以在其上结合，并且使用提供快速信号传播的短通孔制成的各个晶片中的电路元件和连接焊盘之间的连接以及提供比在芯片边缘上提供更多的连接。

27. 发明申请

US20090244954A1 STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS 有权
标题翻译：改善存储容量对单一事件的可靠性的结构和方法
公开(公告)号：US20090244954A1
公开(公告)日：2009-10-01
申请号：US12055509
申请日：2008-03-26
申请人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
发明人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
IPC分类号： G11C11/40 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , G11C11/4125 , H01L27/0921 , H01L27/1104 , H01L29/66181 , H03K3/0375
摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).
摘要翻译：数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

28. 发明授权

US5729052A Integrated ULSI heatsink 失效
标题翻译：集成ULSI散热器
公开(公告)号：US5729052A
公开(公告)日：1998-03-17
申请号：US667210
申请日：1996-06-20
申请人： William R. Tonti , Jack A. Mandelman , Jerzy M. Zalesinski , Toshiharu Furukawa , Son V. Nguyen , Dureseti Chidambarrao
发明人： William R. Tonti , Jack A. Mandelman , Jerzy M. Zalesinski , Toshiharu Furukawa , Son V. Nguyen , Dureseti Chidambarrao
IPC分类号： H01L21/60 , H01L23/367 , H01L29/06 , H01L29/34 , H01L23/34
CPC分类号： H01L24/27 , H01L23/367 , H01L24/32 , H01L24/83 , H01L29/0657 , H01L29/34 , H01L2224/03505 , H01L2224/04026 , H01L2224/16225 , H01L2224/16227 , H01L2224/32057 , H01L2224/32059 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/8319 , H01L2224/83385 , H01L2224/83801 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10158 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/181 , Y10S438/928 , Y10S438/964
摘要： A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) followed by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips. The heatsink itself is prepared by first optionally roughening the surface and metalizing the backside of the heatsink with metal interlayer. Next, the chip is thermally attached to the heatsink by reflowing the thermally conductive reflowable material.
摘要翻译：简单且低成本的ULSI集成散热器通过将散热材料集成到硅晶片中更有效地从硅封装中去除热量，将现有的二维技术转化为三维。高功率集成ULSI封装和散热器的制造开始于制造集成电路晶片，直到将晶片切割成单个芯片。晶片的正面受到保护，而晶片的背面露出。暴露的背面通过化学和/或机械过程粗糙化。任选地，然后执行吸气过程以除去杂质。然后将粗糙的背面涂覆有金属中间层，优选铝（Al），随后涂覆铬（Cr）。一层铜（Cu）任选地涂覆在金属夹层上。高度导电的可回流材料，例如焊料或金共晶，沉积在金属夹层上。此时，晶片被切割成芯片。散热器本身通过首先任选地使表面粗糙化并用金属中间层金属化散热器的背面来制备。接下来，通过回流导热的可回流材料将芯片热连接到散热器。

29. 发明申请

US20080157202A1 SOFT ERROR REDUCTION OF CMOS CIRCUITS ON SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION USING BURIED RECOMBINATION CENTERS 有权
标题翻译：使用BURIED重组中心使用混合晶体方位的基板上CMOS电路的软错误减少
公开(公告)号：US20080157202A1
公开(公告)日：2008-07-03
申请号：US11618346
申请日：2006-12-29
申请人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger , Jack A. Mandelman , William Tonti
发明人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger , Jack A. Mandelman , William Tonti
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L29/1083
摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.
摘要翻译：公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。可以形成多个掩埋复合层。可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

30. 发明授权

US06555891B1 SOI hybrid structure with selective epitaxial growth of silicon 有权
公开(公告)号：US06555891B1
公开(公告)日：2003-04-29
申请号：US09690674
申请日：2000-10-17
申请人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
发明人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L27/10894 , H01L21/76262 , H01L21/76264 , H01L21/76278 , H01L21/84 , H01L27/10861 , H01L27/1207
摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

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