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21. 发明授权

US06453399B2 Semiconductor memory device and computer having a synchronization signal indicating that the memory data output is valid 失效
标题翻译：具有指示存储器数据输出有效的同步信号的半导体存储器件和计算机
公开(公告)号：US06453399B2
公开(公告)日：2002-09-17
申请号：US08844949
申请日：1997-04-23
申请人： Tomohisa Wada
发明人： Tomohisa Wada
IPC分类号： G06F1200
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1069 , G11C2207/2245
摘要： A computer includes a storage device having a plurality of memory cells, being operable to output data stored in the memory cell corresponding to an address signal, and being operable to output a data output fixing signal attaining a predetermined level in response to output of the data, and a processing device operable to apply the address signal to the storage device, take in the data from the storage device in response to the fact that the data output fixing signal attains the predetermined level, and perform processing in accordance with the data. The storage device and the processing device may be formed on a single chip. The processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapse of a maximum access time determined in a specification prescribed taking the worst conditions into consideration.
摘要翻译：计算机包括具有多个存储器单元的存储装置，可操作以输出存储在对应于地址信号的存储单元中的数据，并且可操作以响应于数据的输出而输出达到预定电平的数据输出固定信号以及可操作以将地址信号施加到存储装置的处理装置，响应于数据输出固定信号达到预定电平的事实从存储装置接收数据，并根据该数据进行处理。存储装置和处理装置可以形成在单个芯片上。每当输出数据输出固定信号时，处理装置可以接收和处理数据。当存储装置在比最差条件更好的条件下运行时，可以在经过考虑到最差条件规定的规格中确定的最大访问时间之前执行数据处理。

22. 发明授权

US6008674A Semiconductor integrated circuit device with adjustable high voltage detection circuit 失效
标题翻译：具有可调高压检测电路的半导体集成电路器件
公开(公告)号：US6008674A
公开(公告)日：1999-12-28
申请号：US927796
申请日：1997-09-11
申请人： Tomohisa Wada , Masaaki Mihara , Yasuhiko Taito , Yoshikazu Miyawaki , Katsumi Dosaka
发明人： Tomohisa Wada , Masaaki Mihara , Yasuhiko Taito , Yoshikazu Miyawaki , Katsumi Dosaka
IPC分类号： G11C16/06 , G05F1/56 , G05F3/24 , G11C5/14 , G11C11/407 , H03K5/153
CPC分类号： G11C5/147 , G05F3/242
摘要： A semiconductor integrated circuit device with a high voltage detection circuit comprises a high voltage step-down circuit for stepping down a high voltage input and outputting the stepped-down voltage, a reference voltage generator for generating plural reference voltages, a reference voltage selector for selecting one of the plural reference voltages, a high voltage detection circuit for comparing the stepped down voltage with the selected reference voltage to detect a high voltage and a control circuit for controlling the voltage drop of the high voltage and selection of the plural reference voltages to set the high voltage to be detected by the high voltage detector. There is also disclosed semiconductor integrated circuit having a high voltage step-down circuit for outputting plural stepped-down voltages having a fine tuner for fine-tuning each of the plural stepped-down voltages wherein a stepped-down voltage having been tuned finely is compared with a reference voltage given by a reference voltage generator.
摘要翻译：具有高电压检测电路的半导体集成电路装置包括用于降压高压输入并输出降压的高压降压电路，用于产生多个参考电压的参考电压发生器，用于选择的参考电压选择器多个参考电压中的一个，用于将降压电压与所选择的参考电压进行比较以检测高电压的高电压检测电路，以及用于控制高电压的电压降和选择多个参考电压的控制电路以设置由高电压检测器检测的高电压。还公开了一种具有高压降压电路的半导体集成电路，用于输出具有微调整器的多个降压电压，用于微调多个降压电压中的每一个，其中比较精调的降压电压具有由参考电压发生器给出的参考电压。

23. 发明授权

US5966324A Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells 失效
标题翻译：静态半导体存储器件通过由相邻存储器单元共享的双极晶体管驱动位线电位
公开(公告)号：US5966324A
公开(公告)日：1999-10-12
申请号：US896333
申请日：1997-07-17
申请人： Tomohisa Wada , Yutaka Arita
发明人： Tomohisa Wada , Yutaka Arita
IPC分类号： G11C11/411 , G11C11/412 , H01L27/10 , H01L27/11 , G11C11/34
CPC分类号： H01L27/1112 , G11C11/412
摘要： Memory cells which are adjacent to each other along a column direction share a bipolar transistor driving the potential level of a corresponding bit line. Other memory cells which are adjacent to each other in the column direction share another bipolar transistor driving the potential level of another corresponding bit line. Each bipolar transistor drives the potential level of the corresponding bit line in response to storage information of a selected memory cell, whereby data can be read at a high speed with a low power supply voltage.
摘要翻译：沿着列方向彼此相邻的存储单元共享驱动相应位线的电位的双极晶体管。在列方向上彼此相邻的其他存储单元共享驱动另一对应位线的电位电平的另一双极晶体管。每个双极晶体管响应于所选择的存储单元的存储信息驱动相应位线的电位电平，由此可以以低电源电压高速读取数据。

24. 发明授权

US5929539A Semiconductor memory device adaptable to external power supplies of different voltage levels 失效
标题翻译：半导体存储器件适用于不同电压等级的外部电源
公开(公告)号：US5929539A
公开(公告)日：1999-07-27
申请号：US897614
申请日：1997-07-21
申请人： Kunihiko Kozaru , Tomohisa Wada
发明人： Kunihiko Kozaru , Tomohisa Wada
IPC分类号： G11C11/413 , G05F1/46 , G11C5/14 , G11C8/08 , G11C11/407 , H02J1/10
CPC分类号： G11C5/14 , G05F1/465 , G11C5/147 , G11C8/08 , Y10T307/675 , Y10T307/696 , Y10T307/724 , Y10T307/858
摘要： A semiconductor memory device includes a plurality of external power supply pads P1 to P3. Connection between external power supply pads P1 to P3 and an external power supply is determined in accordance with the voltage of the external power supply to be used, and the connection is switched by bonding. External power supply of a high voltage level is connected to an external power supply pad P2 which is connected to VDC1 and VDC2. A circuit including memory cells operates using the voltage applied from VDC1 or external power supply pad P3, while a group of word line drivers operates using the voltage applied from VDC2 or external power supply pad P1. VDC1 down converts the external power supply voltage, and VDC2 down converts it in accordance with the level of the voltage of the external power supply voltage, and generates internal power supply voltages, respectively. Accordingly, a semiconductor memory device which operates adapted to different external power supplies can be obtained.
摘要翻译：半导体存储器件包括多个外部电源焊盘P1至P3。根据要使用的外部电源的电压来确定外部电源焊盘P1至P3与外部电源之间的连接，并且通过焊接切换连接。高电压电平的外部电源连接到连接到VDC1和VDC2的外部电源焊盘P2。包括存储单元的电路使用从VDC1或外部电源焊盘P3施加的电压进行工作，而一组字线驱动器使用从VDC2或外部电源焊盘P1施加的电压进行操作。 VDC1下降转换外部电源电压，VDC2根据外部电源电压的电平降低转换，分别产生内部电源电压。因此，可以获得适用于不同外部电源的半导体存储器件。

25. 发明授权

US5886388A Static semiconductor memory device and manufacturing method thereof 失效
标题翻译：静态半导体存储器件及其制造方法
公开(公告)号：US5886388A
公开(公告)日：1999-03-23
申请号：US10473
申请日：1998-01-21
申请人： Tomohisa Wada , Hirotada Kuriyama
发明人： Tomohisa Wada , Hirotada Kuriyama
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/11 , H01L27/12 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： NMOS transistors as well as pMOS transistors are formed in an SOI layer. One of the impurity diffusion regions of the transistors are respectively connected. A longitudinal end of polysilicon layer extends in one direction to be connected to one of the impurity diffusion regions of transistor. A longitudinal end of a polysilicon layer extends in a direction which is opposite from the above mentioned one direction to be connected to one of the impurity diffusion regions of transistor. As a result, the area for a memory cell region in a static semiconductor memory device can be reduced, and the interconnection structure can be simplified.
摘要翻译： NMOS晶体管以及pMOS晶体管形成在SOI层中。分别连接晶体管的杂质扩散区域之一。多晶硅层的纵向端部在一个方向上延伸以连接到晶体管的一个杂质扩散区域。多晶硅层的纵向端部沿与上述一个方向相反的方向延伸，以连接到晶体管的一个杂质扩散区域。结果，可以减少静态半导体存储器件中的存储单元区域的面积，并且可以简化互连结构。

26. 发明授权

US5850367A Static type semiconductor memory with latch circuit amplifying read data read on a sub bit line pair and transferring the amplified read data to a main bit line pair and operation method thereof 失效
标题翻译：具有锁存电路的静态型半导体存储器，放大在子位线对上读取的读取数据，并将放大的读取数据传送到主位线对及其操作方法
公开(公告)号：US5850367A
公开(公告)日：1998-12-15
申请号：US815986
申请日：1997-03-10
申请人： Tomohisa Wada , Yoshiyuki Haraguchi
发明人： Tomohisa Wada , Yoshiyuki Haraguchi
IPC分类号： G11C11/41 , G11C11/419 , G11C8/00
CPC分类号： G11C11/419
摘要： A static type semiconductor memory device includes a main bit line pair, and a plurality of memory blocks connected to the main bit line pair. Each of the memory blocks includes a local bit line pair, a static memory connected to the local bit line pair, an amplifier which amplifies potential difference between the paired local bit lines, and a data transfer gate which transfers data between the local bit line pair and the main bit line pair.
摘要翻译：静态半导体存储器件包括主位线对和连接到主位线对的多个存储器块。每个存储块包括本地位线对，连接到本地位线对的静态存储器，放大成对的局部位线之间的电位差的放大器和在本地位线对之间传送数据的数据传输门和主位线对。

27. 发明授权

US5134585A Circuit for repairing defective bit in semiconductor memory device and repairing method 失效
标题翻译：用于修复半导体存储器件中的有缺陷的电路和修复方法
公开(公告)号：US5134585A
公开(公告)日：1992-07-28
申请号：US500965
申请日：1990-03-29
申请人： Shuji Murakami , Tomohisa Wada , Kenji Anami
发明人： Shuji Murakami , Tomohisa Wada , Kenji Anami
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04
CPC分类号： G11C29/848 , G11C29/70
摘要： A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and no program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.

28. 发明授权

US4879690A Static random access memory with reduced soft error rate 失效
标题翻译：具有降低软错误率的静态随机存取存储器
公开(公告)号：US4879690A
公开(公告)日：1989-11-07
申请号：US231063
申请日：1988-08-11
申请人： Kenji Anami , Katsuki Ichinose , Tomohisa Wada
发明人： Kenji Anami , Katsuki Ichinose , Tomohisa Wada
IPC分类号： G11C5/00 , G11C11/412
CPC分类号： G11C11/4125 , G11C5/005
摘要： A storage node in each of memory cells in a static RAM is connected to a bit line through an accessing MOSFET. The accessing MOSFET has its gate connected to a word line. A word line driver comprising a level shifting N channel MOSFET and a CMOS inverter is connected to the word line. At the time of selecting the word line, a potential which is lower, by a threshold voltage of the MOSFET, than a power-supply potential is applied to the word line. Thus, a sub-threshold current flowing in the MOSFET connected between the storage node for storing data at a high level and the bit line to which data of a high level is read out becomes substantially small, so that a potential of the storage node for storing data of a high level is not lowered.
摘要翻译：静态RAM中每个存储单元中的存储节点通过访问MOSFET连接到位线。存取MOSFET的栅极连接到字线。包括电平移位N沟道MOSFET和CMOS反相器的字线驱动器连接到字线。在选择字线时，对字线施加低于MOSFET的阈值电压的电位低于电源电位的电位。因此，在连接在用于存储高电平的数据的存储节点和读出高电平的数据的位线之间的MOSFET中流动的子阈值电流变得基本上小，从而存储节点的电位存储高电平的数据不降低。

29. 发明授权

US4751683A Static semiconductor memory device comprising word lines each operating at three different voltage levels 失效
标题翻译：静态半导体存储器件包括各自以三个不同电压电平工作的字线
公开(公告)号：US4751683A
公开(公告)日：1988-06-14
申请号：US771709
申请日：1985-09-03
申请人： Tomohisa Wada , Hirofumi Shinohara
发明人： Tomohisa Wada , Hirofumi Shinohara
IPC分类号： G11C11/34 , G11C8/08 , G11C8/18 , G11C8/00
CPC分类号： G11C8/08 , G11C8/18
摘要： A semiconductor memory device in accordance with the present invention operates in response to an address transition detection (ATD) signal for detecting a change in an x address as well as to a write enable signal WE to make the signal level on a selected word line vary according to the read mode and the write mode, whereby dissipation of electric power can be reduced.
摘要翻译：根据本发明的半导体存储器件响应于用于检测x地址变化的地址转换检测（ATD）信号以及写入使能信号和上拉沿W而在所选择的字线上产生信号电平根据读取模式和写入模式而变化，从而可以减少功率耗散。

30. 发明授权

US06519187B2 Semiconductor memory device having read data multiplexer 失效
标题翻译：具有读数据多路复用器的半导体存储器件
公开(公告)号：US06519187B2
公开(公告)日：2003-02-11
申请号：US09960973
申请日：2001-09-25
申请人： Tomohisa Wada
发明人： Tomohisa Wada
IPC分类号： G11C710
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1012 , G11C7/1027 , G11C7/1039 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C8/00 , G11C2207/2218 , G11C2207/2245
摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by a latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for externally output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputer, large size calculators, work stations and personal computers can be improved.
摘要翻译：与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。在不从存储单元阵列读出数据的期间，由锁存电路取入写入数据。比较器比较保持的内部地址信号和用于读取数据的内部地址信号。如果在它们之间找到匹配，则多路复用器从锁存电路输出数据以进行外部输出。因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓冲存储器的高速操作以及诸如超级计算机等各种级别的计算机的速度性能，大型计算器，工作站和个人计算机可以改进。

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