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21. 发明授权

US5175704A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5175704A
公开(公告)日：1992-12-29
申请号：US607468
申请日：1990-10-31
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34
CPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34
摘要： In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.
摘要翻译：在非易失性半导体存储器件中，布线层连接在电源和存储单元之间。布线层的电阻大于负载晶体管的导通电阻，负载晶体管基本上决定负载特性。因此，载荷特性曲线在倾斜度上更为平缓，形状更为直线。这使得数据写入操作对于形成存储单元的制造的晶体管的沟道长度的变化是稳定的。

22. 发明授权

US4831592A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US4831592A
公开(公告)日：1989-05-16
申请号：US68521
申请日：1987-07-01
申请人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
发明人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
IPC分类号： G11C16/30 , G11C16/32
CPC分类号： G11C16/32 , G11C16/30
摘要： A nonvolatile semiconductor memory device includes a pulse signal generator for applying a pulse signal to a capacitor, a first diode connected at an anode to the capacitor, a charging circuit for charging the capacitor in a programming mode, a voltage limiter for preventing a potential at the output node from increasing above a predetermined level, memory cells of nonvolatile MOS transistors, a load MOS transistor connected to a high-voltage terminal, a row decoder for selecting a set of memory cells arranged in one row, column gate MOS transistors connected between respective sets of memory cells arranged in one column and the load MOS transistor, a data generator responsive to the voltage at the output node to turn on or off the load MOS transistor, and a column decoder responsive to the voltage at the output node to selectively energize the column gate MOS transistors. It further comprises a second diode connected between the cathode of the first diode and the output node, and a discharging circuit for discharging the cathode of the first diode to a reference voltage level during a time other than a programming mode.
摘要翻译：一种非易失性半导体存储器件，包括用于向电容器施加脉冲信号的脉冲信号发生器，连接到电容器的阳极的第一二极管，以编程模式对电容器充电的充电电路，用于防止电位输出节点从预定电平上升，非易失性MOS晶体管的存储单元，连接到高电压端子的负载MOS晶体管，用于选择排列成一行的一组存储单元的行解码器，连接在设置在一列中的各组存储单元和负载MOS晶体管，响应于输出节点处的电压以打开或关闭负载MOS晶体管的数据发生器，以及响应于输出节点处的电压以选择性地激励列栅极MOS晶体管。其还包括连接在第一二极管的阴极和输出节点之间的第二二极管和用于在编程模式之外的时间期间将第一二极管的阴极放电到参考电压电平的放电电路。

23. 发明授权

US5055706A Delay circuit that resets after pulse-like noise 失效
标题翻译：脉冲状噪声后复位的延迟电路
公开(公告)号：US5055706A
公开(公告)日：1991-10-08
申请号：US311798
申请日：1989-02-17
申请人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Shigeru Kumagai
发明人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Shigeru Kumagai
IPC分类号： H01L21/8238 , G11C11/407 , G11C11/4076 , H01L27/092 , H01L27/10 , H03K5/00 , H03K5/1252 , H03K5/13 , H03K5/131 , H03K5/133 , H03K5/134 , H03K5/135
CPC分类号： H03K5/133 , H03K5/1252 , H03K2005/00195
摘要： A semiconductor integrated circuit including delay means for generating an output signal delayed by a predetermined time with respect to an input signal when a logic level of said input signal changes in a first direction. The delay means receives a control signal and generates an internal control signal which is delayed by a predetermined time with respect to the control signal when a logic level of the control signal changes in a first direction, including a capacitor for delaying the control signal and a resistor having one end and having the other end connected to the capacitor.
摘要翻译：一种半导体集成电路，包括延迟装置，用于当所述输入信号的逻辑电平在第一方向上变化时，产生相对于输入信号延迟预定时间的输出信号。当控制信号的逻辑电平在第一方向上变化时，延迟装置接收控制信号并产生相对于控制信号延迟预定时间的内部控制信号，包括用于延迟控制信号的电容器和电阻器具有一端并且另一端连接到电容器。

24. 发明授权

US6122193A Non-volatile semiconductor memory capable of storing 1-bit data or multi-bit data 有权
标题翻译：能够存储1位数据或多位数据的非易失性半导体存储器
公开(公告)号：US6122193A
公开(公告)日：2000-09-19
申请号：US323455
申请日：1999-06-01
申请人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
发明人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5642
摘要： Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.
摘要翻译：数据锁存电路是从执行读取或程序的选择存储器单元提供的。数据锁存电路分为两组。当2位数据从选择存储单元读取或编程到选择存储单元中时，通过选择信号选择一个数据锁存电路，当读取或编程1位数据时，一组中的两个数据锁存电路由选择信号。在一个或两个选择的数据锁存电路和数据输入/输出缓冲器之间，交换数据。通过这样做，有可能在二级数据与有关程序的多级（4级或更多级）数据之间切换或将数据读入或取出存储单元变成可能。

25. 发明授权

US06418052B1 Nonvolatile semiconductor memory equipped with data latch circuits for transferring one-bit data or multi-bit data 有权
标题翻译：非易失性半导体存储器配备有用于传送一位数据或多位数据的数据锁存电路
公开(公告)号：US06418052B1
公开(公告)日：2002-07-09
申请号：US09976826
申请日：2001-10-12
申请人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
发明人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
IPC分类号： G11C1624
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5642
摘要： Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.
摘要翻译：数据锁存电路是从执行读取或程序的选择存储器单元提供的。数据锁存电路分为两组。当2位数据从选择存储单元读取或编程到选择存储单元中时，通过选择信号选择一个数据锁存电路，当读取或编程1位数据时，一组中的两个数据锁存电路由选择信号。在一个或两个选择的数据锁存电路和数据输入/输出缓冲器之间，交换数据。通过这样做，有可能在二级数据与有关程序的多级（4级或更多级）数据之间切换或将数据读入或取出存储单元变成可能。

26. 发明授权

US5682346A Nonvolatile semiconductor memory device having suitable writing efficiency 失效
标题翻译：具有合适写入效率的非易失性半导体存储器件
公开(公告)号：US5682346A
公开(公告)日：1997-10-28
申请号：US626256
申请日：1996-03-29
申请人： Toshio Yamamura , Hiroto Nakai , Tomoharu Tanaka
发明人： Toshio Yamamura , Hiroto Nakai , Tomoharu Tanaka
IPC分类号： G11C16/10 , G11C16/30 , G11C11/34
CPC分类号： G11C16/30 , G11C16/10
摘要： According to the present invention, a voltage level for boosting a writing voltage to be supplied to memory cells of a memory cell array, and writing time are optimized in consideration of writing efficiency and a distribution of threshold voltage. A boosting circuit boosts the writing voltage to be supplied to memory cells. A counter counts the number of writing times in accordance with a signal of a timer. The timer outputs the signal used to count the number of writing times at a fixed interval from a first writing time until an arbitrary writing time in counting a predetermined number of writing times by the counter and to count the number of writing times at an interval when the number of writing times is gradually increased after the arbitrary writing time in order to control supplying time of the writing voltage to the memory cells. Additionally, a voltage control circuit gradually divides a boost level due to the boosting circuit in accordance with the arbitrary number of writing times until the writing voltage reaches a predetermined upper limit, and maintains the writing voltage when the writing voltage reaches the predetermined upper limit.
摘要翻译：根据本发明，考虑到写入效率和阈值电压的分布，优化用于升压提供给存储单元阵列的存储单元的写入电压和写入时间的电压电平。升压电路提高写入电压以供给存储单元。计数器根据定时器的信号对写入次数进行计数。定时器输出用于对从计数器计数预定写入次数的第一写入时间到任意写入时间之间的固定间隔计数写入时间的信号，并以一定间隔对写入次数进行计数，在任意写入时间之后，写入次数逐渐增加，以便控制向存储单元提供写入电压的时间。此外，电压控制电路根据升压电路根据任意的写入次数逐渐分割升压电平，直到写入电压达到预定上限，并且当写入电压达到预定上限时保持写入电压。

27. 发明授权

US06331945B1 Non-volatile semiconductor memory capable of storing one-bit data or multi-bit data 有权
标题翻译：能够存储一位数据或多位数据的非易失性半导体存储器
公开(公告)号：US06331945B1
公开(公告)日：2001-12-18
申请号：US09528112
申请日：2000-03-17
申请人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
发明人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5642
摘要： Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.
摘要翻译：数据锁存电路是从执行读取或程序的选择存储器单元提供的。数据锁存电路分为两组。当2位数据从选择存储单元读取或编程到选择存储单元中时，通过选择信号选择一个数据锁存电路，当读取或编程1位数据时，一组中的两个数据锁存电路由选择信号。在一个或两个选择的数据锁存电路和数据输入/输出缓冲器之间，交换数据。通过这样做，有可能在二级数据与有关程序的多级（4级或更多级）数据之间切换或将数据读入或取出存储单元变成可能。

28. 发明授权

US5073726A Input circuit of semiconductor integrated circuit and semiconductor integrated circuit having input circuit 失效
标题翻译：具有输入电路的半导体集成电路和半导体集成电路的输入电路
公开(公告)号：US5073726A
公开(公告)日：1991-12-17
申请号：US559139
申请日：1990-07-30
申请人： Hideo Kato , Shinichi Kikuchi , Hiroto Nakai , Hiroshi Iwahashi
发明人： Hideo Kato , Shinichi Kikuchi , Hiroto Nakai , Hiroshi Iwahashi
IPC分类号： H03K19/0185 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00384 , H03K19/00361
摘要： There is disclosed a semiconductor integrated circuit provided with an input circuit including an N-channel MOS transistor of which threshold voltage is set to a value lower than those of N-channel MOS transistors constituting other internal circuits of the integrated circuit. Thus, a circuit having a high operating margin for power supply noises is provided. This circuit further comprises a P-channel MOS transistor constituting a portion of a NOR gate or a NAND gate together with the above-mentioned N-channel MOS transistor.

29. 发明授权

US08892810B2 Semiconductor device and memory protection method 有权
标题翻译：半导体器件和存储器保护方法
公开(公告)号：US08892810B2
公开(公告)日：2014-11-18
申请号：US13399185
申请日：2012-02-17
申请人： Hiroto Nakai , Tatsunori Kanai , Kenichi Maeda
发明人： Hiroto Nakai , Tatsunori Kanai , Kenichi Maeda
IPC分类号： G06F12/02 , G06F9/54
CPC分类号： G06F9/524 , G06F9/544 , G06F12/0246
摘要： According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.
摘要翻译：根据一个实施例，半导体器件包括处理器和存储器件。存储器件具有非易失性半导体存储器件，并且被配置为用作处理器的主存储器。当处理器执行多个程序时，处理器管理作为各个程序的工作流程执行程序所需的信息，并创建表，其保持各工作组所需的信息和各条信息的地址之间的关系在存储器件中，用于各个工作台。处理器参考相应工作台的相应表访问存储器件。

30. 发明授权

US08400816B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US08400816B2
公开(公告)日：2013-03-19
申请号：US13237500
申请日：2011-09-20
申请人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
发明人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
摘要翻译：电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

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