专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4697101A Read/write control circuit 失效
标题翻译：读/写控制电路
公开(公告)号：US4697101A
公开(公告)日：1987-09-29
申请号：US645392
申请日：1984-08-29
申请人： Hiroshi Iwahashi , Masamichi Asano , Masaki Momodomi , Hidenobu Minagawa , Kazuto Suzuki , Akira Narita
发明人： Hiroshi Iwahashi , Masamichi Asano , Masaki Momodomi , Hidenobu Minagawa , Kazuto Suzuki , Akira Narita
IPC分类号： G11C16/12 , G11C16/30 , H03K19/096 , G06F7/38 , H03K17/16
CPC分类号： G11C16/30 , G11C16/12
摘要： A semiconductor integrated circuit which has a CMOS inverter formed of p- and n-channel MOSFETs, and a D-type n-channel MOSFET coupled at the gate to the output terminal of the CMOS inverter, having one end coupled to a high voltage terminal and the other end coupled to the drain of the p-channel MOSFET.
摘要翻译：一种半导体集成电路，其具有由p-沟道MOSFET和n沟道MOSFET形成的CMOS反相器，以及在栅极处连接到CMOS反相器的输出端的D型n沟道MOSFET，其一端耦合到高电压端子另一端耦合到p沟道MOSFET的漏极。

2. 发明授权

US4819212A Nonvolatile semiconductor memory device with readout test circuitry 失效
标题翻译：具有读出测试电路的非易失性半导体存储器件
公开(公告)号：US4819212A
公开(公告)日：1989-04-04
申请号：US50717
申请日：1987-05-18
申请人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
发明人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
IPC分类号： G11C8/12 , G11C16/08 , G11C7/00 , G11C7/02 , G11C8/00
CPC分类号： G11C8/12 , G11C16/08
摘要： A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each including a nonvolatile transistor, a plurality of row lines each connected to the memory cells arranged on a corresponding row, a plurality of column lines connected to the memory cells arranged on a corresponding column, an address buffer circuit for receiving external address signals at its address input terminal and for outputting internal address signals in response to the received external address signals, column line-select transistors connected to the column lines, a column-decoding circuit for selectively biasing the column line-select transistors, a row-decoding circuit for selectively biasing the row lines, and data-detecting circuit for detecting the potential of the column line selected by the column line-select transistor. The device further includes a control unit generating a control signal for controlling the address buffer circuit so that the internal address signal is set at a predetermined value, to set all the row lines in a non-selected state, thereby setting a column line, selected by the column line-select transistor, at a predetermined potential.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，每个存储单元包括非易失性晶体管，多个行线，各行连接到布置在相应行上的存储器单元，多个列线连接到布置的存储单元在对应的列上，地址缓冲电路，用于在其地址输入端接收外部地址信号，并响应于所接收的外部地址信号输出内部地址信号，连接到列线的列线选择晶体管，列解码电路用于选择性地偏置列线选择晶体管，用于选择性地偏置行线的行解码电路，以及用于检测由列线选择晶体管选择的列线的电位的数据检测电路。该装置还包括控制单元，其产生用于控制地址缓冲电路的控制信号，使得内部地址信号被设置为预定值，以将所有行线设置为未选择状态，从而设置列线通过列线选择晶体管，以预定电位。

3. 发明申请

US20110123640A1 NOVEL FERMENTED MILK PRODUCT AND USE THEREOF 审中-公开
标题翻译：新型发酵奶制品及其用途
公开(公告)号：US20110123640A1
公开(公告)日：2011-05-26
申请号：US12996917
申请日：2009-06-08
申请人： Yoshie Yabumoto , Hisanori Tani , Kazuto Suzuki , Tetsumi Yabumoto , Yuriko Yoshida
发明人： Yoshie Yabumoto , Hisanori Tani , Kazuto Suzuki , Tetsumi Yabumoto , Yuriko Yoshida
IPC分类号： A61K35/20 , C12N1/20 , A61P1/00 , A61P31/00 , A23C9/127
CPC分类号： A23L3/3463 , A23C9/127 , A23L33/135 , A23Y2220/47 , A61K35/74 , A61K36/064 , A61K2300/00
摘要： Disclosed is a fermented milk product, which is useful for the promotion of good health. The fermented milk product is produced by fermenting a milk raw material with a combination of microorganisms consisting of (1) Lactobacillus kefiri and (2) at least one microorganism selected from the group consisting of Kazachstania turicensis, Kazachstania unispora and Kluyveromyces marxianus. Preferably, the fermented milk product is produced by fermenting the milk raw material with a combination of microorganisms consisting of at least Lactobacillus kefiri strain P-IF, Lactobacillus kefiri strain P-B1, Kazachstania turicensis strain P-Y3, Kazachstania unispora strain P-Y4 and Kluyveromyces marxianus strain P-Y5.
摘要翻译：公开了一种用于促进身体健康的发酵乳制品。发酵乳产品是通过用（1）乳酸杆菌和（2）至少一种选自以下的微生物组合的微生物发酵牛奶原料来制造的：（2）至少一种选自哈萨克斯坦土地，哈萨克斯坦和马克斯克鲁维酵母的微生物。优选地，发酵乳产品是通过用至少包含克氏杆菌菌株P-IF，乳杆菌菌株P-B1，卡斯卡齐亚山茱萸菌株P-Y3，单孢子菌株P-Y4组成的微生物组合来发酵乳制品马克斯克鲁维酵母菌株P-Y5。

4. 发明授权

US4831592A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US4831592A
公开(公告)日：1989-05-16
申请号：US68521
申请日：1987-07-01
申请人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
发明人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
IPC分类号： G11C16/30 , G11C16/32
CPC分类号： G11C16/32 , G11C16/30
摘要： A nonvolatile semiconductor memory device includes a pulse signal generator for applying a pulse signal to a capacitor, a first diode connected at an anode to the capacitor, a charging circuit for charging the capacitor in a programming mode, a voltage limiter for preventing a potential at the output node from increasing above a predetermined level, memory cells of nonvolatile MOS transistors, a load MOS transistor connected to a high-voltage terminal, a row decoder for selecting a set of memory cells arranged in one row, column gate MOS transistors connected between respective sets of memory cells arranged in one column and the load MOS transistor, a data generator responsive to the voltage at the output node to turn on or off the load MOS transistor, and a column decoder responsive to the voltage at the output node to selectively energize the column gate MOS transistors. It further comprises a second diode connected between the cathode of the first diode and the output node, and a discharging circuit for discharging the cathode of the first diode to a reference voltage level during a time other than a programming mode.
摘要翻译：一种非易失性半导体存储器件，包括用于向电容器施加脉冲信号的脉冲信号发生器，连接到电容器的阳极的第一二极管，以编程模式对电容器充电的充电电路，用于防止电位输出节点从预定电平上升，非易失性MOS晶体管的存储单元，连接到高电压端子的负载MOS晶体管，用于选择排列成一行的一组存储单元的行解码器，连接在设置在一列中的各组存储单元和负载MOS晶体管，响应于输出节点处的电压以打开或关闭负载MOS晶体管的数据发生器，以及响应于输出节点处的电压以选择性地激励列栅极MOS晶体管。其还包括连接在第一二极管的阴极和输出节点之间的第二二极管和用于在编程模式之外的时间期间将第一二极管的阴极放电到参考电压电平的放电电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式