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21. 发明授权

US07348838B2 Method and system for DC offset cancellation from a modulated signal 有权
标题翻译：用于调制信号的直流偏移消除的方法和系统
公开(公告)号：US07348838B2
公开(公告)日：2008-03-25
申请号：US11115199
申请日：2005-04-27
申请人： Sumant Ranganathan , Tom W. Kwan , Hung-Sung Li
发明人： Sumant Ranganathan , Tom W. Kwan , Hung-Sung Li
IPC分类号： H03D3/00 , H03L5/00
CPC分类号： H04B1/30
摘要： Provided are a method and system for removing an offset direct current (DC) component from an input waveform. The method includes multiplying the input waveform with a demodulation waveform to produce a first differential current signal. An absolute value representation of the demodulation waveform is multiplied with a reference DC offset value to produce a second differential current signal. The first and second differential current signals are then differenced.
摘要翻译：提供了用于从输入波形去除偏移直流（DC）分量的方法和系统。该方法包括将输入波形与解调波形相乘以产生第一差分电流信号。将解调波形的绝对值表示与参考DC偏移值相乘以产生第二差分电流信号。然后，第一和第二差分电流信号被差分。

22. 发明授权

US07092043B2 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US07092043B2
公开(公告)日：2006-08-15
申请号：US09439101
申请日：1999-11-12
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/455
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

23. 发明授权

US06937177B2 Shuffler apparatus and related dynamic element matching technique for linearization of unit-element digital-to-analog converters 失效
标题翻译：用于线性化单元数模转换器的洗牌器和相关动态元件匹配技术
公开(公告)号：US06937177B2
公开(公告)日：2005-08-30
申请号：US10847459
申请日：2004-05-18
申请人： Tom W. Kwan
发明人： Tom W. Kwan
IPC分类号： H03M1/06 , H03M1/74 , H03M1/66
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/502
摘要： A data shuffler apparatus shuffles input bits to perform dynamic element matching. The shuffler apparatus includes N input shufflers, each input shuffler having N input terminals and N output terminals, each input terminal of each input shuffler receiving a respective one of the input bits. The apparatus also includes N output shufflers, each output shuffler having N input terminals and N output terminals, the input and output shufflers being interconnected such that each of the N output terminals of each input shuffler is connected to a respective input terminal of a different one of the N output shufflers.
摘要翻译：数据洗牌装置洗牌输入位以执行动态元素匹配。洗牌装置包括N个输入洗牌器，每个输入洗牌器具有N个输入端和N个输出端，每个输入洗牌者的每个输入端接收相应的一个输入比特。该装置还包括N个输出混洗器，每个输出洗牌器具有N个输入端子和N个输出端子，输入和输出洗牌器互连，使得每个输入洗牌器的N个输出端子中的每一个连接到不同的输入端子的相应输入端子的N输出洗牌机。

24. 发明授权

US5786778A Variable sample-rate DAC/ADC/converter system 失效
标题翻译：可变采样率DAC / ADC /转换器系统
公开(公告)号：US5786778A
公开(公告)日：1998-07-28
申请号：US539438
申请日：1995-10-05
申请人： Robert W. Adams , Tom W. Kwan
发明人： Robert W. Adams , Tom W. Kwan
IPC分类号： H03H17/06 , H03L7/18 , H03M3/02 , H03M1/66
CPC分类号： H03L7/1806 , H03H17/06 , H03H17/0614 , H03H17/0657
摘要： A digital oversampling noise-shaping system includes a digital noise-shaped clock signal generating circuit, including a DCO operating at a fixed master clock rate, that receives a digital input sample clock signal having an input sample rate and produces a noise-shaped clock signal having a variable rate with an average rate equal to a multiple of the input sample rate. In one embodiment, an interpolator is coupled to the clock signal generating circuit and receives the digital input samples at an input sample rate and, responsive to the noise-shaped clock signal, upsamples the digital input samples at the variable rate. A hold circuit repeats the interpolated samples at the master clock rate. A digital noise-shaping circuit, coupled to the hold circuit, performs digital noise-shaping on the repeated samples received from the hold circuit. In another embodiment, a decimator is coupled to the clock signal generating circuit. Digital input samples having an input sample rate are latched to the input of the decimator at a rate controlled by the noise-shaped clock signal. The clock signal generating circuit includes a PLL in one embodiment. The digital noise-shaping circuit, in one embodiment, includes sigma-delta modulator in which the downstream one of first and second integrators operates at a reduced multiple of a fixed master clock rate.
摘要翻译：数字过采样噪声整形系统包括数字噪声形状的时钟信号发生电路，其包括以固定的主时钟速率工作的DCO，其接收具有输入采样率的数字输入采样时钟信号，并产生噪声形状的时钟信号具有平均速率等于输入采样率的倍数的可变速率。在一个实施例中，内插器耦合到时钟信号发生电路，并以输入采样率接收数字输入采样，并响应于噪声形状的时钟信号以可变速率对数字输入采样进行上采样。保持电路以主时钟速率重复插值样本。耦合到保持电路的数字噪声整形电路对从保持电路接收的重复样本执行数字噪声整形。在另一个实施例中，抽取器耦合到时钟信号发生电路。具有输入采样率的数字输入样本以噪声形状的时钟信号控制的速率被锁存到抽取器的输入端。时钟信号发生电路在一个实施例中包括PLL。在一个实施例中，数字噪声整形电路包括Σ-Δ调制器，其中第一和第二积分器中的下游一个以固定主时钟速率的减少的倍数工作。

25. 发明授权

US5475628A Asynchronous digital sample rate converter 失效
公开(公告)号：US5475628A
公开(公告)日：1995-12-12
申请号：US954149
申请日：1992-09-30
申请人： Robert W. Adams , Tom W. Kwan , Michael Coln
发明人： Robert W. Adams , Tom W. Kwan , Michael Coln
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06 , G06F17/17
CPC分类号： H03H17/0628
摘要： An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

26. 发明授权

US08441381B2 Gate leakage compensation in a current mirror 有权
标题翻译：电流镜中的门漏电补偿
公开(公告)号：US08441381B2
公开(公告)日：2013-05-14
申请号：US13246319
申请日：2011-09-27
申请人： Ovidiu Bajdechi , Tom W. Kwan
发明人： Ovidiu Bajdechi , Tom W. Kwan
IPC分类号： H03M1/00
CPC分类号： G05F3/08 , G05F3/267 , H03M1/0607 , H03M1/66
摘要： A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding reference source without any substantial affect upon its full scale output.
摘要翻译：公开了一种用于补偿在数模转换器（DAC）的电流镜中具有非常薄的氧化物层的薄氧化物器件的栅极泄漏电流的方法和装置。 DAC将数字输入信号从数字信号域中的数字表示转换为模拟信号域中的模拟表示，以提供模拟输出信号。 DAC使用一个或多个晶体管将数字输入信号从数字表示转换为模拟表示。这些晶体管通常使用具有与这些非常薄的氧化物层相关联的非常薄的氧化物层和相应的栅极泄漏电流的薄氧化物器件来实现。电流导向DAC提供独立于其相应参考源的这些栅极泄漏电流，而对其满量程输出没有任何实质影响。

27. 发明授权

US08045066B2 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US08045066B2
公开(公告)日：2011-10-25
申请号：US12883575
申请日：2010-09-16
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/455 , H04N5/44
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

28. 发明授权

US07821581B2 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US07821581B2
公开(公告)日：2010-10-26
申请号：US12219925
申请日：2008-07-30
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/455
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

29. 发明授权

US07598808B2 Gigabit ethernet transceiver with analog front end 有权
标题翻译：具有模拟前端的千兆以太网收发器
公开(公告)号：US07598808B2
公开(公告)日：2009-10-06
申请号：US12037797
申请日：2008-02-26
申请人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03G3/10
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
摘要翻译：电路从集成电路可编程增益衰减器中的信号路径中去除开关。可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。这种开关可能在信号中引入非线性。通过将开关与信号路径隔离，可以提高PGA的线性度。

30. 发明授权

US07477100B2 Method and system for single ended to differential ended demodulation 有权
标题翻译：单端到差分端解调的方法和系统
公开(公告)号：US07477100B2
公开(公告)日：2009-01-13
申请号：US11115191
申请日：2005-04-27
申请人： Sumant Ranganathan , Tom W. Kwan , Hung-Sung Li
发明人： Sumant Ranganathan , Tom W. Kwan , Hung-Sung Li
IPC分类号： H03D3/00
CPC分类号： G01R27/2605 , G01D5/24
摘要： Provided are a method and system for demodulating a signal. The method includes receiving the signal along first and second signal paths within a demodulator having a common starting point. Impedance values along each of the paths are changed alternately in synchronism.
摘要翻译：提供一种用于解调信号的方法和系统。该方法包括沿着具有公共起始点的解调器中的第一和第二信号路径接收信号。沿着每个路径的阻抗值交替地同步地改变。

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