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21. 发明授权

US06825526B1 Structure for increasing drive current in a memory array and related method 有权
标题翻译：用于增加存储器阵列中的驱动电流的结构和相关方法
公开(公告)号：US06825526B1
公开(公告)日：2004-11-30
申请号：US10759809
申请日：2004-01-16
申请人： Yue-Song He , Nian Yang , Zhigang Wang
发明人： Yue-Song He , Nian Yang , Zhigang Wang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： According to one exemplary embodiment, a memory array comprises first and second isolation regions situated in a substrate, where the first and second isolation regions are separated by a separation distance. The memory array further comprises a trench situated between the first and second isolation regions, where the trench defines trench sidewalls and a trench bottom in the substrate. The memory array further comprises a tunnel oxide layer situated between the first and second isolation regions, where the tunnel oxide layer is situated on the trench sidewalls and the trench bottom. According to this embodiment, the memory array further comprises a channel region situated underneath the tunnel oxide layer and extending along the trench sidewalls and the trench bottom, where the channel region has an effective channel width, where the effective channel width increases as a height of the trench sidewalls increases.
摘要翻译：根据一个示例性实施例，存储器阵列包括位于衬底中的第一和第二隔离区域，其中第一和第二隔离区域被分离距离。存储器阵列还包括位于第一和第二隔离区之间的沟槽，其中沟槽限定衬底中的沟槽侧壁和沟底。存储器阵列还包括位于第一和第二隔离区之间的隧道氧化物层，其中隧道氧化物层位于沟槽侧壁和沟槽底部。根据该实施例，存储器阵列还包括位于隧道氧化物层下方并沿着沟槽侧壁和沟槽底部延伸的沟道区，其中沟道区具有有效沟道宽度，其中有效沟道宽度随着沟槽侧壁增加。

22. 发明授权

US06777957B1 Test structure to measure interlayer dielectric effects and breakdown and detect metal defects in flash memories 失效
标题翻译：用于测量层间电介质效应和击穿并检测闪存中的金属缺陷的测试结构
公开(公告)号：US06777957B1
公开(公告)日：2004-08-17
申请号：US10174734
申请日：2002-06-18
申请人： Nian Yang , Zhigang Wang , John Jianshi Wang
发明人： Nian Yang , Zhigang Wang , John Jianshi Wang
IPC分类号： G01R2726
CPC分类号： H01L27/11521 , G11C16/04 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , H01L22/34 , H01L27/115 , H01L2924/3011
摘要： An apparatus for testing a dielectric property of a material constituting the interlayer dielectric of a flash memory device is formed by a layer (122) of the dielectric material disposed throughout a test structure (200) representative of the flash memory device and a plurality of conductors (117A, 117B, 117C) disposed within that layer (122) or a pair of planar conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509) deposited such that the conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509) are substantially parallel to each other and the layer (122) of dielectric material is disposed throughout a test structure (400, 500) so as to separate the conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509), the test structure (400, 500) functioning as a capacitor. The apparatus may also test a conductive property of a material constituting the conducting lines of a flash memory device by disposing a conductor (801, 901) through the dielectric material (122).
摘要翻译：用于测试构成闪速存储器件的层间电介质的材料的介电性能的装置由设置在表示闪速存储器件的测试结构（200）内的介电材料层（122）和多个导体（122A），或者一对平面导体（402,404; 502,503,504,505,506,507,508,509），这些导体（402,404） ; 502,503,504,505,506,507,508,509,506,507,508,505,506,507,508,505,505,505,508,505,509,506,507,508,505,509,508,509,508,509,508,509,505,505,509,508,509,508,509,505,505,509,505,505,509,505,505,509,505,505,509,50 所述测试结构（400,500）用作电容器，所述测试结构（400,500）用作电容器（402,404; 502,503,504,505,506,507,508,509）。该设备还可以通过将电介质材料（122）布置在导体（801,901）上来测试构成闪存器件的导线的材料的导电性能。

23. 发明授权

US06696331B1 Method of protecting a stacked gate structure during fabrication 有权
标题翻译：在制造期间保护堆叠栅极结构的方法
公开(公告)号：US06696331B1
公开(公告)日：2004-02-24
申请号：US10217807
申请日：2002-08-12
申请人： Nian Yang , Zhigang Wang , Hsiao-Han Thio
发明人： Nian Yang , Zhigang Wang , Hsiao-Han Thio
IPC分类号： H01L218238
CPC分类号： H01L21/28273 , H01L29/42324
摘要： A method of protecting a stacked gate structure of a flash memory device during fabrication is disclosed. Additionally, the manner of protecting the stacked gate structure during fabrication is simple to implement and is cost-effective. In particular, a protective layer is deposited on the stacked gate structure to protect the stacked gate structure before a resist removal process is performed a second time. Despite undergoing two resist removal processes, the stacked gate structure suffers less damage than the convention fabrication techniques, increasing the yield and reliability of the flash memory device.
摘要翻译：公开了一种在制造期间保护闪存器件的堆叠栅极结构的方法。此外，在制造期间保护堆叠栅极结构的方式易于实现并且是成本有效的。特别地，在堆叠的栅极结构上沉积保护层，以在第二次执行抗蚀剂去除处理之前保护堆叠的栅极结构。尽管经历了两次抗蚀剂去除工艺，堆叠的栅极结构比常规的制造技术遭受的损坏更小，从而提高了闪存器件的产量和可靠性。

24. 发明授权

US06643185B1 Method for repairing over-erasure of fast bits on floating gate memory devices 有权
标题翻译：修复浮动栅极存储器件上快速位擦除的方法
公开(公告)号：US06643185B1
公开(公告)日：2003-11-04
申请号：US10215140
申请日：2002-08-07
申请人： Zhigang Wang , Nian Yang , Jiang Li
发明人： Zhigang Wang , Nian Yang , Jiang Li
IPC分类号： G11C1604
CPC分类号： G11C16/3404
摘要： A method for repairing over-erasure of floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for performing a program disturb operation on an array of memory cells for repairing over-erasure of fast bits. The program disturb operation is applied simultaneously to the entire array making it compatible with channel erase schemes. The fast bits are programmed back to a normal state above 0 Volts by applying a substrate voltage to a substrate common to the array of memory cells. A gate voltage is applied to a plurality of word lines coupled to control gates of said array of memory cells. A program pulse time for applying voltages ranges from approximately 10 microseconds to 1 second. A voltage differential between a control gate and the substrate in a memory cell is in the range of approximately 9 Volts to about 20 Volts.
摘要翻译：一种用于修复浮动栅极存储器件的过度擦除的方法。具体地，本发明的一个实施例公开了一种用于对用于修复快速位的擦除的存储器单元阵列执行编程干扰操作的方法。编程干扰操作同时应用于整个阵列，使其与信道擦除方案兼容。通过将衬底电压施加到存储器单元阵列共用的衬底上，快速位被编程回0伏以上的正常状态。栅极电压被施加到耦合到所述存储器单元阵列的控制栅极的多个字线。用于施加电压的编程脉冲时间范围从大约10微秒到1秒。存储器单元中的控制栅极和衬底之间的电压差在大约9伏至大约20伏的范围内。

25. 发明授权

US06642106B1 Method for increasing core gain in flash memory device using strained silicon 有权
标题翻译：使用应变硅提高闪存器件的磁芯增益的方法
公开(公告)号：US06642106B1
公开(公告)日：2003-11-04
申请号：US10159323
申请日：2002-05-31
申请人： Nian Yang , Hyeon-Seag Kim , Zhigang Wang
发明人： Nian Yang , Hyeon-Seag Kim , Zhigang Wang
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/26506 , H01L27/115 , H01L27/11521 , H01L29/1054 , H01L29/7842 , H01L29/7881 , Y10S438/933 , Y10S438/938
摘要： A method of memory device fabrication. In one embodiment, the method of memory device (400) fabrication comprises implanting an element (200) in a substrate (440). The element (200) causes an inherent elongational realignment of atoms in silicon (101,102) when silicon (100) is formed (471) upon the substrate (440) with the element (200) implanted therein. A layer of silicon (100) is formed (471) on the substrate having the element (200) implanted therein (470), wherein alignment of atoms (101) of the silicon elongates (102) to an atomical alignment equivalent (101g) to said element (200). The layer of silicon (471) and the substrate (470) are crystallized subsequent to the elongational realignment of atoms of the layer of silicon (101g), wherein a crystallized layer of elongated silicon (101g) decreases electron scattering thus realizing increase core gain in the memory device (400).
摘要翻译：一种存储器件制造方法。在一个实施例中，存储器件（400）制造的方法包括将元件（200）植入衬底（440）中。当元件（200）注入到衬底（440）上时，当硅（100）形成（471）时，元件（200）引起硅（101,102）中的原子的固有伸长重新对准。在其上注入有元素（200）的衬底（470）上形成硅（100）层（471），其中硅延长材料（102）的原子（101）与原子对准当量（101g）之间的取向与所述元件（200）。在硅层（101g）的原子的伸长重新对准之后，硅层（471）和衬底（470）被结晶，其中细长硅（101g）的结晶层减少电子散射，从而实现增加核心增益存储器件（400）。

26. 发明授权

US06590260B1 Memory device having improved programmability 失效
标题翻译：存储器件具有改进的可编程性
公开(公告)号：US06590260B1
公开(公告)日：2003-07-08
申请号：US10103077
申请日：2002-03-20
申请人： Nian Yang , John Jianshi Wang , Zhigang Wang
发明人： Nian Yang , John Jianshi Wang , Zhigang Wang
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： A method for enhancing the operating characteristics of memory devices (400C), such as flash memory devices, by manipulating the Fermi energy levels of the substrate (406) and the floating gate (404). In so doing, the gap between the minimum conduction band energy level (408) and the Fermi energy level (412) of the floating gate (404) is extended so as to readily facilitate the movement of electrons from the substrate (406) into the floating gate (404).
摘要翻译：一种用于通过操纵衬底（406）和浮动栅极（404）的费米能级来增强诸如闪存器件的存储器件（400C）的操作特性的方法。在这样做时，浮动栅极（404）的最小导带能量水平（408）和费米能级（412）之间的间隙被延伸，以便容易地促进电子从衬底（406）移动到浮动门（404）。

27. 发明授权

US06898124B1 Efficient and accurate sensing circuit and technique for low voltage flash memory devices 有权
标题翻译：高效，准确的低压闪存器件感测电路和技术
公开(公告)号：US06898124B1
公开(公告)日：2005-05-24
申请号：US10678446
申请日：2003-10-03
申请人： Zhigang Wang , Nian Yang , Yue-Song He
发明人： Zhigang Wang , Nian Yang , Yue-Song He
IPC分类号： G11C11/56 , G11C16/06 , G11C16/26
CPC分类号： G11C16/26 , G11C11/5642
摘要： An exemplary sensing circuit comprises a first transistor connected to a first node, where a target memory cell has a drain capable of being connected to the first node through a selection circuit during a read operation involving the target memory cell. The sensing circuit further comprises a decouple circuit which is connected to the first transistor. The decouple circuit includes a second transistor having a gate coupled to a gate of the first transistor. The decouple circuit further has a decouple coefficient (N) greater than 1. The drain of the second transistor is connected at a second node to a reference voltage through a bias resistor. With the arrangement, the drain of the second transistor generates a sense amp input voltage at the second node such that the sense amp input voltage is decoupled from the first node.
摘要翻译：示例性感测电路包括连接到第一节点的第一晶体管，其中目标存储器单元具有能够在涉及目标存储器单元的读取操作期间通过选择电路连接到第一节点的漏极。感测电路还包括连接到第一晶体管的去耦电路。解耦电路包括具有耦合到第一晶体管的栅极的栅极的第二晶体管。去耦电路还具有大于1的去耦系数（N）。第二晶体管的漏极通过偏置电阻器在第二节点连接到参考电压。利用该布置，第二晶体管的漏极在第二节点处产生感测放大器输入电压，使得感测放大器输入电压与第一节点分离。

28. 发明授权

US06828623B1 Floating gate memory device with homogeneous oxynitride tunneling dielectric 有权
标题翻译：具有均匀氧氮化物隧道电介质的浮栅存储器件
公开(公告)号：US06828623B1
公开(公告)日：2004-12-07
申请号：US10232487
申请日：2002-08-30
申请人： Xin Guo , Nian Yang , Zhigang Wang
发明人： Xin Guo , Nian Yang , Zhigang Wang
IPC分类号： H01L29788
CPC分类号： H01L29/518 , H01L21/28273 , H01L29/7885
摘要： A memory device with homogeneous oxynitride tunneling dielectric. Specifically, the present invention describes a flash memory cell that includes a tunnel oxide dielectric layer including homogeneous oxynitride. The tunnel oxide dielectric layer separates a floating gate from a channel region that is formed between a source region and a drain region in a substrate. The flash memory cell further includes a dielectric layer that separates a control gate from the floating gate. In one case, the homogenous oxynitride is a defect free silicon nitride. The homogeneity of the oxynitride is due to the uniform distribution of nitride within the tunnel oxide dielectric layer. Further, the use of the homogeneous oxynitride can increase the dielectric constant and lower the barrier height of the tunnel oxide dielectric layer for increased performance. Also, the homogenous oxynitride supports source-side channel hot hole erasing in the flash memory cell.
摘要翻译：具有均匀氧氮化物隧道电介质的存储器件。具体地，本发明描述了一种闪存单元，其包括包括均匀氮氧化物的隧道氧化物介电层。隧道氧化物电介质层将浮置栅极与形成在衬底中的源极区域和漏极区域之间的沟道区域分离。闪存单元还包括将控制栅极与浮动栅极分离的介质层。在一种情况下，均匀的氮氧化合物是无缺陷的氮化硅。氧氮化物的均匀性是由于氮化物在隧道氧化物介电层内的均匀分布。此外，为了提高性能，使用均匀的氮氧化物可以增加介电常数并降低隧道氧化物介电层的势垒高度。此外，均匀的氮氧化物支持闪存单元中的源极侧通道热孔擦除。

29. 发明授权

US06822259B1 Method of detecting and distinguishing stack gate edge defects at the source or drain junction 有权
标题翻译：在源极或漏极结处检测和区分堆叠栅极边缘缺陷的方法
公开(公告)号：US06822259B1
公开(公告)日：2004-11-23
申请号：US10126193
申请日：2002-04-19
申请人： Zhigang Wang , Nian Yang , Xin Guo
发明人： Zhigang Wang , Nian Yang , Xin Guo
IPC分类号： H01L2358
CPC分类号： H01L21/28273 , G11C16/04 , G11C29/006 , G11C2029/0403 , G11C2029/5002
摘要： A method and apparatus for testing semiconductors comprising stacked floating gate structures. A floating gate is programmed (710). An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions (720). Subsequent to the stressing, a drain current versus gate voltage relationship is measured (730). The sequence of programming, stressing and measuring may be repeated (740) with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge-defect may be identified (750) as associated with a source edge or a drain edge. In this novel manner, stack gate edge defects may be identified and localized via non-destructive means, and corrective actions to the semiconductor manufacturing process and/or the partially manufactured wafer may be taken.
摘要翻译：一种用于测试包括堆叠浮栅结构的半导体的方法和装置。浮动门被编程（710）。电应力或干扰电压在特定条件（720）中用源极和漏极施加到控制栅极。在应力之后，测量漏极电流与栅极电压的关系（730）。编程，应力和测量的顺序可以重复（740），具有不同的源和漏源条件。更具体地，在将源极保持在地面的同时将漏极保持在接地处时，将正和负偏压施加到源极，并且在将源保持在地面的同时将类似的偏压施加到漏极。通过检查在该应力应用序列之后采取的测量信息，可以将源极边缘或漏极边缘的叠栅极边缘缺陷识别（750）。以这种新颖的方式，可以通过非破坏性手段识别和定位堆叠栅极边缘缺陷，并且可以采取对半导体制造工艺和/或部分制造的晶片的校正动作。

30. 发明授权

US06797650B1 Flash memory devices with oxynitride dielectric as the charge storage media 有权
标题翻译：具有氧氮化物介质的闪存器件作为电荷存储介质
公开(公告)号：US06797650B1
公开(公告)日：2004-09-28
申请号：US10342032
申请日：2003-01-14
申请人： Zhigang Wang , Nian Yang , John Jianshi Wang , Jiang Li
发明人： Zhigang Wang , Nian Yang , John Jianshi Wang , Jiang Li
IPC分类号： H01L2131
CPC分类号： H01L21/28202 , H01L21/28273 , H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/513 , H01L29/518
摘要： One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si3N4)x(SiO2)(1-x), where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.
摘要翻译：本发明的一个方面涉及将电荷存储在基本上化学计量的氮氧化硅电介质中的闪存器件。化学计量的氮氧化硅电介质可由式（Si 3 N 4）x（SiO 2）（1-x）表示，其中x为0-1。基本上化学计量的氮氧化硅电介质具有不符合上述公式的相对较少的原子。本发明的闪速存储器件具有比可比较的SONOS型闪存器件更少的缺陷和更低的泄漏。本发明的另一方面涉及通过FTIR，折射率测量或两者的组合来评估化学计量。

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