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21. 发明授权

US08716081B2 Capacitor top plate over source/drain to form a 1T memory device 有权
标题翻译：源极/漏极上的电容器顶板形成1T存储器件
公开(公告)号：US08716081B2
公开(公告)日：2014-05-06
申请号：US11686475
申请日：2007-03-15
申请人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
发明人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
IPC分类号： H01L29/76
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/1085 , H01L27/11
摘要： A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.
摘要翻译：用于诸如1T-SRAM的存储器件的方法和结构，其具有直接在掺杂底板区域上方的电容器顶板。示例设备包括以下。形成为围绕衬底上的有源区域的隔离膜。形成在有源区域的一部分上的栅极电介质和栅电极。与栅电极相邻的衬底中的源极元件和漏极元件。漏极元件由漏区和底板区组成。漏极区域位于底板区域和栅极结构之间。电容器电介质和电容器顶板在底板区域的至少部分上方。

22. 发明授权

US07737009B2 Method of implanting a non-dopant atom into a semiconductor device 有权
标题翻译：将非掺杂剂原子注入到半导体器件中的方法
公开(公告)号：US07737009B2
公开(公告)日：2010-06-15
申请号：US11836008
申请日：2007-08-08
申请人： Richard Lindsay , Yong Meng Lee , Manfred Eller
发明人： Richard Lindsay , Yong Meng Lee , Manfred Eller
IPC分类号： H01L21/265
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/76237 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.
摘要翻译：公开了一种形成隔离沟槽结构的方法，该方法包括在与隔离区相关联的半导体本体中形成隔离沟槽，并将非掺杂剂原子注入到隔离沟槽中，从而形成一个区域以修改光刻轮廓半导体体。随后，隔离沟槽填充有电介质材料。

23. 发明授权

US07615427B2 Spacer-less low-k dielectric processes 有权
标题翻译：无隔离低k介电过程
公开(公告)号：US07615427B2
公开(公告)日：2009-11-10
申请号：US11447565
申请日：2006-06-05
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

24. 发明申请

US20080315317A1 SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS 审中-公开
标题翻译：具有补充应变通道的半导体系统
公开(公告)号：US20080315317A1
公开(公告)日：2008-12-25
申请号：US11767449
申请日：2007-06-22
申请人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
发明人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/31155 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66606 , H01L29/7843
摘要： A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.
摘要翻译：提供一种半导体系统，包括提供半导体衬底; 在半导体衬底中形成PMOS和NMOS晶体管; 在半导体衬底上形成拉伸应变层; 并放宽PMOS晶体管周围的拉伸应变层。

25. 发明申请

US20080048269A1 METHOD OF FABRICATING STRUCTURE FOR INTEGRATED CIRCUIT INCORPORATING HYBRID ORIENTATION TECHNOLOGY AND TRENCH ISOLATION REGIONS 审中-公开
标题翻译：整合电路结合混合方向技术与热分解区域的方法
公开(公告)号：US20080048269A1
公开(公告)日：2008-02-28
申请号：US11467325
申请日：2006-08-25
申请人： Xiangdong Chen , Yong Meng Lee
发明人： Xiangdong Chen , Yong Meng Lee
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/823878 , H01L27/0922
摘要： An embodiment of the present invention discloses a method of fabricating a structure for an integrated circuit incorporating hybrid orientation technology (HOT) and trench isolation regions. The structure of the integrated circuit comprising: a substrate with a first silicon layer of a first crystalline orientation and a second silicon layer, of a second crystalline orientation different from the first crystalline orientation, disposed on the first silicon layer; a dielectric layer on the substrate; a first silicon active trench region, having first crystalline orientation, extending to the first silicon layer; a second silicon active trench region, having the second crystalline orientation, extending to the second silicon layer, the first silicon active region electrically isolated from the second silicon active region by a portion of the dielectric layer; a first transistor on the first silicon active region; and a second transistor on the second silicon active region.
摘要翻译：本发明的实施例公开了一种制造用于集成混合取向技术（HOT）和沟槽隔离区域的集成电路的结构的方法。所述集成电路的结构包括：设置在所述第一硅层上的具有第一晶体取向的第一硅层和与所述第一晶体取向不同的第二晶体取向的第二硅层的衬底; 基底上的电介质层; 具有第一晶体取向的第一硅有源沟槽区，延伸到第一硅层; 具有第二晶体取向的第二硅有源沟槽区延伸到第二硅层，第一硅有源区通过介电层的一部分与第二硅有源区电隔离; 在第一硅有源区上的第一晶体管; 以及在第二硅有源区上的第二晶体管。

26. 发明授权

US07256084B2 Composite stress spacer 有权
标题翻译：复合应力间隔
公开(公告)号：US07256084B2
公开(公告)日：2007-08-14
申请号：US11122667
申请日：2005-05-04
申请人： Khee Yong Lim , Wenhe Lin , Chung Woh Lai , Yong Meng Lee , Liang Choo Hsia , Young Way Teh , John Sudijono , Wee Leng Tan , Hui Peng Koh
发明人： Khee Yong Lim , Wenhe Lin , Chung Woh Lai , Yong Meng Lee , Liang Choo Hsia , Young Way Teh , John Sudijono , Wee Leng Tan , Hui Peng Koh
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.
摘要翻译：示例性方法实施例形成在PFET和NFET区域上在衬底上产生拉伸应力的间隔物。我们形成PFET和NFET栅极，并在PFET和NFET栅极上形成拉伸间隔物。我们将第一离子注入拉伸的PFET间隔物中以形成中和的应力PFET间隔物。中和的应力PFET间隔物减轻了由衬底上的拉伸应力间隔物产生的拉伸应力。这提高了设备性能。

27. 发明授权

US06511884B1 Method to form and/or isolate vertical transistors 有权
标题翻译：形成和/或隔离垂直晶体管的方法
公开(公告)号：US06511884B1
公开(公告)日：2003-01-28
申请号：US09972503
申请日：2001-10-09
申请人： Elgin Quek , Ravi Sundaresan , Yang Pan , Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
发明人： Elgin Quek , Ravi Sundaresan , Yang Pan , Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a second implanted region is formed within the vertical pillar selected from the group consisting of a drain region and a source region that is not the same as the first implanted region to complete formation of the isolated vertical transistor.
摘要翻译：一种制造隔离垂直晶体管的方法，包括以下步骤。提供具有从包括源极区域和漏极区域的组中选择的第一注入区域的晶片。该晶片还包括在中心晶体管区域两侧的STI区域。将晶片图案化到第一注入区域，以使用图案化的硬掩模在中心晶体管区域内形成垂直柱。具有侧壁的立柱。在晶片上形成衬垫介质层，衬在垂直柱上。在焊盘介电层上形成氮化物层。该结构被图案化并蚀刻通过氮化物层和焊盘介电层; 并进入STI区域内的晶片，以在晶片内形成STI沟槽。 STI沟槽填充有绝缘材料，以在STI沟槽内形成STI。图案化的氮化物和焊盘介电层被去除。去除图案化的硬掩模。栅极氧化物生长在晶片和垂直柱的暴露部分上。在垂直柱的栅极氧化物衬里侧壁上形成间隔栅极。间隔栅极内部形成间隔栅极，并且在垂直柱内形成第二注入区，该垂直柱选自由漏极区域和不同于第一注入区域的源极区域组成的组，以完成孤立的垂直晶体管。

28. 发明授权

US6107140A Method of patterning gate electrode conductor with ultra-thin gate oxide 有权
标题翻译：具有超薄栅氧化层的栅电极导体图形化方法
公开(公告)号：US6107140A
公开(公告)日：2000-08-22
申请号：US467131
申请日：1999-12-20
申请人： Yong Meng Lee , Yunqiang Zhang
发明人： Yong Meng Lee , Yunqiang Zhang
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66583 , H01L21/28167 , H01L21/28194 , H01L21/28211
摘要： A method of patterning a gate electrode comprising the following steps. A semiconductor structure, with an upper silicon layer, and having an active area is provided. A sacrificial oxide layer overlies the semiconductor structure, a first polysilicon layer overlies the sacrificial silicon oxide layer, and a silicon nitride layer overlies the polysilicon layer. The nitride, first poly, and sacrificial oxide layers are patterned to form a gate conductor opening within the active area. A gate oxide layer is grown over the semiconductor structure within the gate conductor opening an oxide sidewall spacers are grown on the first polysilicon sidewalls. A second polysilicon layer is deposited over the structure, filling the gate conductor opening. The second polysilicon layer is polished to remove the excess of the second polysilicon layer from the nitride layer, forming a polysilicon gate conductor within the gate conductor opening and over the gate oxide layer. The polysilicon gate conductor has an exposed upper surface that is oxidized to form a hard mask oxide layer over the polysilicon gate conductor. The nitride layer is etched and removed from the first polysilicon layer. The first polysilicon layer is etched and removed. The oxide sidewalls and hard mask are removed.
摘要翻译：一种图案化栅电极的方法，包括以下步骤。提供具有上硅层并且具有有源区的半导体结构。牺牲氧化物层覆盖半导体结构，第一多晶硅层覆盖牺牲氧化硅层，氮化硅层覆盖多晶硅层。将氮化物，第一聚氧化物层和牺牲氧化物层图案化以在有源区域内形成栅极导体开口。栅极氧化物层生长在栅极导体开口内的半导体结构上，氧化物侧壁间隔物生长在第一多晶硅侧壁上。在结构上沉积第二多晶硅层，填充栅极导体开口。抛光第二多晶硅层以从氮化物层去除多余的第二多晶硅层，在栅极导体开口内和栅极氧化物层上形成多晶硅栅极导体。多晶硅栅极导体具有暴露的上表面，其被氧化以在多晶硅栅极导体上形成硬掩模氧化物层。氮化物层被蚀刻并从第一多晶硅层去除。蚀刻并除去第一多晶硅层。去除氧化物侧壁和硬掩模。

29. 发明申请

US20140004677A1 High-k Seal for Protection of Replacement Gates 审中-公开
标题翻译：用于保护更换闸门的高k密封
公开(公告)号：US20140004677A1
公开(公告)日：2014-01-02
申请号：US13537140
申请日：2012-06-29
申请人： Ying Li , Raymond Joy , Yong Meng Lee
发明人： Ying Li , Raymond Joy , Yong Meng Lee
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/66636 , H01L21/823814 , H01L29/66545 , H01L29/66606 , H01L29/78
摘要： Embodiments of the invention include methods of protecting sacrificial gates during raised/source drain and replacement metal gate processes. Embodiments include steps of forming sacrificial gates on a semiconductor substrate, protecting the sacrificial gates with gate seals, forming source/drains near the sacrificial gates without substantially growing semiconductor material on the sacrificial gates, removing the gate seals, and replacing the sacrificial gates with metal gates. In some embodiments, the gate seals are made of a high-k material.
摘要翻译：本发明的实施例包括在升高/源极漏极和替换金属栅极工艺期间保护牺牲栅极的方法。实施例包括在半导体衬底上形成牺牲栅极的步骤，用栅极密封保护牺牲栅极，在牺牲栅极附近形成源极/漏极，而不在牺牲栅极上基本上生长半导体材料，移除栅极密封件，并用金属替换牺牲栅极大门在一些实施例中，门密封由高k材料制成。

30. 发明申请

US20110169096A1 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US20110169096A1
公开(公告)日：2011-07-14
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

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