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21. 发明授权

US06897143B2 Method of manufacturing semiconductor device including two-step polishing operation for cap metal 失效
标题翻译：制造半导体器件的方法，包括用于金属帽的两步抛光操作
公开(公告)号：US06897143B2
公开(公告)日：2005-05-24
申请号：US10600568
申请日：2003-06-23
申请人： Hiroshi Toyoda , Hiroyuki Yano , Gaku Minamihaba , Dai Fukushima , Tetsuo Matsuda , Hisashi Kaneko
发明人： Hiroshi Toyoda , Hiroyuki Yano , Gaku Minamihaba , Dai Fukushima , Tetsuo Matsuda , Hisashi Kaneko
IPC分类号： H01L21/304 , H01L21/3105 , H01L21/321 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/31053 , H01L21/3212 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.
摘要翻译：形成盖膜的方法包括以R 1的选择性（=盖膜的去除速率/绝缘膜的去除速率）进行抛光操作的第一抛光步骤，以及进行抛光操作的第二抛光步骤 R 2的选择性（=盖膜的去除率/绝缘膜的去除率）。通过使用条件为R 1> R 2的浆料进行每次研磨操作。通过以不同的选择性进行抛光操作，形成了帽膜没有诸如凹陷的盖膜和残留帽膜之间的问题。因此，可以提供具有优异RC特性的半导体器件。

22. 发明授权

US06787827B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06787827B2
公开(公告)日：2004-09-07
申请号：US10132255
申请日：2002-04-26
申请人： Seiji Inumiya , Katsuhiko Hieda , Tetsuo Matsuda , Yoshio Ozawa
发明人： Seiji Inumiya , Katsuhiko Hieda , Tetsuo Matsuda , Yoshio Ozawa
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545 , H01L29/6659
摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成在半导体衬底的围绕着具有第一侧壁绝缘膜的伪栅极图案的部分上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极胶片形成在凹槽中。

23. 发明授权

US06342444B1 Method of forming diffusion barrier for copper interconnects 有权
标题翻译：形成铜互连的扩散阻挡层的方法
公开(公告)号：US06342444B1
公开(公告)日：2002-01-29
申请号：US09522595
申请日：2000-03-10
申请人： Kazuyuki Higashi , Noriaki Matsunaga , Hiroshi Toyoda , Akihiro Kajita , Tetsuo Matsuda , Hisashi Kaneko
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Hiroshi Toyoda , Akihiro Kajita , Tetsuo Matsuda , Hisashi Kaneko
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A TiN film is selectively formed as a barrier layer on a Cu metal layer by selective removal of a Ti metal layer on the Si metal layer after the following steps of selectively forming a Si metal layer as an etching mask on an insulation film, forming a trench pattern by selective removal of the insulation film using the Si metal layer, forming a Cu metal layer in the trench pattern with the Si metal layer remained, forming the Ti metal layer on the Si metal layer and the Cu metal layer as a barrier material with a different kind of eutectic reaction with Cu from the reaction with the etching mask by heat-treatment in an atmosphere of nitrogen, and selectively nitriding the Ti metal layer on the Cu metal layer by heat-treatment of the Ti metal layer in an atmosphere of nitrogen.
摘要翻译：通过在绝缘膜上选择性地形成Si金属层作为蚀刻掩模的以下步骤之后，通过选择性地除去Si金属层上的Ti金属层，在Cu金属层上选择性地形成TiN膜作为阻挡层，形成沟槽图案，通过使用Si金属层选择性去除绝缘膜，在沟槽图案中形成具有Si金属层的Cu金属层，在Si金属层上形成Ti金属层，将Cu金属层形成为阻挡材料在氮气气氛中通过热处理与与蚀刻掩模的反应与Cu的不同种类的共晶反应，并且通过在气氛中热处理Ti金属层来选择性地氮化Cu金属层上的Ti金属层的氮气。

24. 发明授权

US5958630A Phase shifting mask and method of manufacturing the same 失效
标题翻译：相移掩模及其制造方法
公开(公告)号：US5958630A
公开(公告)日：1999-09-28
申请号：US953
申请日：1997-12-30
申请人： Koji Hashimoto , Tetsuo Matsuda
发明人： Koji Hashimoto , Tetsuo Matsuda
IPC分类号： G03F1/30 , H01L21/027 , G03F9/00
CPC分类号： G03F1/30
摘要： The present invention is directed to the prevention of a decrease in the resolution of a film shifter-type alternating phase shifting mask, and the complexity of the mask forming step, and discusses the structure of a novel alternating phase shifting mask, and a novel manufacturing method which does not require the etching for forming a shifter. To achieve this object, hydrogen silsesquioxane (flowable oxide (FOX)) is used as the material for the phase shifter. The optical characteristics of this film are very close to those of a quartz substrate, and the property that the in-surface variation (.+-.3 .sigma.) of the thickness is 1% or less, is close to that of SOG (Spin On Glass). The most advantageous aspect of the FOX being used for the mask manufacturing process is that, since the FOX film is etched at the same time as the resist development, with the alkaline developing solution used for etching the resist, there is no need to provide a particular step for etching the shifter.
摘要翻译：本发明涉及防止膜移位器型交替相移掩模的分辨率降低以及掩模形成步骤的复杂性，并且讨论了新颖的交替相移掩模的结构和新颖的制造方法，其不需要用于形成移位器的蚀刻。为了实现该目的，使用氢倍半硅氧烷（可流动氧化物（FOX））作为移相器的材料。该膜的光学特性非常接近于石英基板，其厚度的面内变化（+/- 3西格玛）为1％以下，与SOG接近（Spin On 玻璃）。用于掩模制造工艺的FOX最有利的方面是，由于与抗蚀剂显影同时蚀刻FOX膜，所以使用用于蚀刻抗蚀剂的碱性显影液，不需要提供蚀刻移位器的特定步骤。

25. 发明授权

US3978210A Antibiotic aculeacins 失效
标题翻译：抗生素ACULEACINS
公开(公告)号：US3978210A
公开(公告)日：1976-08-31
申请号：US556190
申请日：1975-03-06
申请人： Kimio Mizuno , Tetsuo Matsuda , Katsumi Asano , Akira Yagi , Masaki Takada , Tetsu Saito , Minoru Toriya , Shuzo Satoi , Kazuo Matsuura
发明人： Kimio Mizuno , Tetsuo Matsuda , Katsumi Asano , Akira Yagi , Masaki Takada , Tetsu Saito , Minoru Toriya , Shuzo Satoi , Kazuo Matsuura
IPC分类号： A01N63/04 , A61K36/06 , C07G11/00 , C12P1/02 , C12P21/00 , A61K35/70
CPC分类号： C07G11/00 , Y10S435/913
摘要： A family of antibiotics active against pathogenic yeasts and fungi comprises aculeacin-A, -B, -C, -D, -E, -F, and -G. These are produced from cultured broth of Aspergillus aculeatus FERM-P 2324.

26. 发明授权

US3960662A Process for the production of 7-amino-cephem compounds 失效
标题翻译：生产7-氨基头孢烯化合物的方法
公开(公告)号：US3960662A
公开(公告)日：1976-06-01
申请号：US543639
申请日：1975-01-23
申请人： Tetsuo Matsuda , Tsutomu Yamaguchi , Tadashiro Fujii , Kunio Matsumoto , Masataka Morishita , Mitsuru Fukushima , Yuzo Shibuya
发明人： Tetsuo Matsuda , Tsutomu Yamaguchi , Tadashiro Fujii , Kunio Matsumoto , Masataka Morishita , Mitsuru Fukushima , Yuzo Shibuya
IPC分类号： C07D501/18 , C12P35/02 , C12D13/06
CPC分类号： C12P35/02 , Y10S435/822 , Y10S435/874
摘要： 7-Amino-cephem compounds are produced from 7-substituted-cephem compounds by the enzymatic action of microorganisms Comamonas sp. SY-77-1 FERM-P 2410 or Pseudomonas ovalis ATCC 950.
摘要翻译： 7-氨基头孢烯化合物由7-取代的头孢烯化合物通过微生物Comamonas sp的酶促作用产生。 SY-77-1 FERM-P 2410或椭圆形假单胞菌ATCC 950。

27. 发明授权

US08067310B2 Semiconductor device and method for manufacturing of same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08067310B2
公开(公告)日：2011-11-29
申请号：US12645908
申请日：2009-12-23
申请人： Tomomi Imamura , Tetsuo Matsuda , Yoshinosuke Nishijo
发明人： Tomomi Imamura , Tetsuo Matsuda , Yoshinosuke Nishijo
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/53209 , H01L21/76852 , H01L21/76883 , H01L21/76885 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.
摘要翻译：一种制造半导体器件的方法，包括：在半导体衬底上形成第一金属层，所述半导体衬底包括扩散层; 在所述第一金属层上形成具有开口的绝缘层; 在绝缘层的开口中的第一金属层上形成第二金属层; 去除绝缘层; 用第三金属层覆盖第二金属层的暴露表面，第三金属层包括电离倾向低于第二金属层的金属; 以及通过使用第三金属层作为掩模去除第一金属层，形成包括第一金属层，第二金属层和第三金属层的电极互连。

28. 发明授权

US07936015B2 Semiconductor device having trenches filled with a semiconductor having an impurity concentration gradient 有权
标题翻译：具有填充有具有杂质浓度梯度的半导体的沟槽的半导体器件
公开(公告)号：US07936015B2
公开(公告)日：2011-05-03
申请号：US12543165
申请日：2009-08-18
申请人： Kenichi Tokano , Tetsuo Matsuda , Wataru Saito
发明人： Kenichi Tokano , Tetsuo Matsuda , Wataru Saito
IPC分类号： H01L29/772
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.
摘要翻译：第一导电类型的单晶半导体层设置在半导体衬底的表面上。在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

29. 发明授权

US07387717B2 Method of performing electrolytic treatment on a conductive layer of a substrate 失效
标题翻译：在基板的导电层上进行电解处理的方法
公开(公告)号：US07387717B2
公开(公告)日：2008-06-17
申请号：US10631726
申请日：2003-08-01
申请人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
发明人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
IPC分类号： C25D7/12
CPC分类号： H01L21/6719 , C25D7/123 , C25D17/001 , C25D17/12 , C25D17/14 , H01L21/2885 , H01L21/67046 , H01L21/67051 , H01L21/6708 , H01L21/6715 , H01L21/6723 , H01L21/76877 , H01L21/76879 , H01L2924/0002 , H05K3/423 , H01L2924/00
摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
摘要翻译：用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。密封材料90接触表面的周缘部分，以水密的方式密封该部分。阴极电极88在与基板接触时通过电流。阴极部38与基板保持部36一体地旋转。电极臂部30在阴极部38的上方，水平且垂直地移动，阳极98面朝下。将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。因此，电镀处理和附带的处理可以通过单个单元进行。

30. 发明申请

US20060197152A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060197152A1
公开(公告)日：2006-09-07
申请号：US11364203
申请日：2006-03-01
申请人： Kenichi Tokano , Tetsuo Matsuda , Wataru Saito
发明人： Kenichi Tokano , Tetsuo Matsuda , Wataru Saito
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.
摘要翻译：第一导电类型的单晶半导体层设置在半导体衬底的表面上。在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

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