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    • 22. 发明授权
    • Low voltage sensing and control of battery referenced transistors in subscriber loop applications
    • 用户环路应用中电池参考晶体管的低电压感测和控制
    • US07643629B2
    • 2010-01-05
    • US11094832
    • 2005-03-30
    • Jerrell P. HeinMarius Goldenberg
    • Jerrell P. HeinMarius Goldenberg
    • H04M1/00H04M9/00
    • H04M19/005
    • A subscriber line interface circuit apparatus includes tip/ring sense circuitry generating a tip sense signal and a ring sense signal from three sensed currents, wherein the tip sense signal and the ring sense signal correspond to subscriber loop tip and ring currents, respectively. In one embodiment, the tip/ring sense circuitry includes a current mirror generating first and second mirrored sense currents from a first sense current proportional to a battery feed node voltage of a subscriber loop. Current differencing circuitry provides the tip sense signal from a difference between the first mirrored sense current and a second sense current associated with a tip line of the subscriber loop. The current differencing circuitry provides the ring sense signal from a difference between the second mirrored sense current and a third sense current associated with a ring line of the subscriber loop.
    • 用户线路接口电路设备包括尖端/环路感测电路,其产生来自三个感测电流的尖端感测信号和环路感测信号,其中尖端感测信号和环路感测信号分别对应于用户环路尖端和环形电流。 在一个实施例中,尖端/环路感测电路包括电流镜,其从与用户环路的电池馈送节点电压成比例的第一感测电流产生第一和第二镜像检测电流。 电流差分电路从第一镜像检测电流和与用户环路的尖端线相关联的第二感测电流之间的差异提供尖端感测信号。 电流差分电路从第二镜像检测电流和与用户环路的环线相关联的第三检测电流之间的差异提供环形感测信号。
    • 24. 发明授权
    • Method and system for sliced integration of flash analog to digital
converters in read channel circuits
    • 读通道电路中闪存模数转换器的集成方法和系统
    • US5990707A
    • 1999-11-23
    • US927122
    • 1997-09-05
    • Marius GoldenbergRussell Croman
    • Marius GoldenbergRussell Croman
    • H03M1/10H03M1/36H03K5/22
    • H03M1/362H03M1/1023
    • A system and method is provided having a flash analog-to-digital converter (ADC) that includes an input signal buffer, a plurality of identical voltage comparators, and a reference generator. A clock signal defines the time instances at which the instantaneous input signal voltage is compared against a plurality of reference voltages generated by the reference generator. The individual comparator consists of a an integrating amplifier stage followed by an analog latching stage and a digital latch. The integrating amplifier input is allowed to track the input signal continuously. The amplifier output voltage is forced to a voltage close to zero before each conversion cycle is initiated by the ADC clock. At the beginning of the conversion cycle, the amplifier output is released and its voltage will follow an excursion related to the integral of the input of the amplifier. At a predefined time moment later, the analog latch is activated. When activated, the analog latch performs a binary decision that exclusively depends on the sign of the amplifier output voltage at the moment of the an analog latch is activation. The analog latch output may be synchronized with the ADC clock with a digital latch. After a latch period, the amplifier and latch may be reset to zero and the comparator is ready to perform another comparison. In this manner, the analog signal is sampled by use of a sliced integration technique which corresponds to an integral of individual slices of the analog input.
    • 提供了具有包括输入信号缓冲器,多个相同的电压比较器和参考发生器的闪存模数转换器(ADC)的系统和方法。 时钟信号定义瞬时输入信号电压与由参考发生器产生的多个参考电压进行比较的时间实例。 单个比较器包括一个积分放大器级,随后是模拟锁存级和数字锁存器。 积分放大器输入允许连续跟踪输入信号。 在每个转换周期由ADC时钟启动之前,放大器输出电压被强制为接近于零的电压。 在转换周期开始时,放大器输出被释放,其电压将跟随与放大器输入的积分相关的偏移。 在预定的时间之后,模拟锁存器被激活。 当激活时,模拟锁存器执行二进制判定,这完全取决于模拟锁存器激活时放大器输出电压的符号。 模拟锁存器输出可以与数字锁存器的ADC时钟同步。 在锁存周期之后,放大器和锁存器可能被复位为零,并且比较器准备好进行另一个比较。 以这种方式,通过使用对应于模拟输入的各个片的积分的切片积分技术对模拟信号进行采样。
    • 30. 发明申请
    • Power Supply with Digital Control Loop
    • 带数字控制回路的电源
    • US20090245504A1
    • 2009-10-01
    • US12060263
    • 2008-04-01
    • Riad WahbyMichael J. MillsJeffrey A. WhaleyMarius GoldenbergIon C. Tesu
    • Riad WahbyMichael J. MillsJeffrey A. WhaleyMarius GoldenbergIon C. Tesu
    • H04M9/00
    • H04M19/001
    • One embodiment of a power supply apparatus includes a first switcher coupled to provide VOUT from a VSUPPLY. A cascaded second switcher is coupled to provide a subscriber line interface circuit target VBAT from VOUT, wherein the first switcher is placed in one of an active mode and an inactive mode in accordance with a function of VSUPPLY and VBAT, wherein in the active mode  VOUT VSUPPLY  ≥ 1 , wherein in the inactive mode VOUT≈VSUPPLY.
    • 电源设备的一个实施例包括耦合以从VSUPPLY提供VOUT的第一切换器。 级联的第二切换器被耦合以从VOUT提供用户线接口电路目标VBAT,其中根据VSUPPLY和VBAT的功能将第一切换器置于活动模式和非活动模式之一中,其中在活动模式< maths id =“MATH-US-00001”num =“00001”> mi> > 其中处于非活动模式VOUT≈VSUPPLY。