专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20120100666A1 PHOTOLUMINESCENCE IMAGE FOR ALIGNMENT OF SELECTIVE-EMITTER DIFFUSIONS 审中-公开
标题翻译：用于选择性发射扩散的对准的光致发光图像
公开(公告)号：US20120100666A1
公开(公告)日：2012-04-26
申请号：US13282219
申请日：2011-10-26
申请人： James M. Gee , Asaf Schlezinger , Marco Galiazzo , Andrea Baccini , Timothy W. Weidman , Sunhom Paak , Hongbin Fang , Zhenhua Zhang
发明人： James M. Gee , Asaf Schlezinger , Marco Galiazzo , Andrea Baccini , Timothy W. Weidman , Sunhom Paak , Hongbin Fang , Zhenhua Zhang
IPC分类号： H01L31/18 , B05C11/00 , B05C13/00
CPC分类号： H01L31/1804 , G03F9/00 , H01L21/67706 , H01L21/67715 , H01L21/6776 , H01L21/681 , H01L21/6838 , H01L31/022425 , Y02E10/547 , Y02P70/521
摘要： Embodiments of the invention generally provide a solar cell formation process that includes the formation of metal contacts over heavily doped regions that are formed in a desired pattern on a surface of a substrate. Embodiments of the invention also provide an inspection system and supporting hardware that is used to reliably position a similarly shaped, or patterned, metal contact structure on the patterned heavily doped regions to allow an Ohmic contact to be made. The metal contact structure, such as fingers and busbars, are formed on the heavily doped regions so that a high quality electrical connection can be formed between these two regions.
摘要翻译：本发明的实施例通常提供一种太阳能电池形成工艺，其包括在基底表面上以所需图案形成的重掺杂区域上形成金属触点。本发明的实施例还提供了一种检查系统和支撑硬件，其用于在图案化的重掺杂区域上可靠地定位类似形状或图案化的金属接触结构，以允许进行欧姆接触。在重掺杂区域上形成诸如指状物和母线的金属接触结构，从而可以在这两个区域之间形成高质量的电连接。

22. 发明授权

US07834659B1 Multi-step programming of E fuse cells 有权
标题翻译： E熔丝电池的多步编程
公开(公告)号：US07834659B1
公开(公告)日：2010-11-16
申请号：US12043103
申请日：2008-03-05
申请人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
发明人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
IPC分类号： H03K19/173
CPC分类号： G11C17/18
摘要： E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fuses to program the selected E-fuse to a second state.
摘要翻译：通过对多个E保险丝应用第一编程脉冲将多个E保险丝编程到第一状态来编程E熔丝存储器阵列中的电子熔丝; 然后将第二编程脉冲施加到所述多个E熔丝中的至少一个选定的E熔丝，以将所选择的E熔丝编程到第二状态。

23. 发明授权

US07746696B1 CMOS twin cell non-volatile random access memory 有权
标题翻译： CMOS双胞晶非易失性随机存取存储器
公开(公告)号：US07746696B1
公开(公告)日：2010-06-29
申请号：US12042266
申请日：2008-03-04
申请人： Sunhom Paak
发明人： Sunhom Paak
IPC分类号： G11C14/00 , G11C11/34
CPC分类号： G11C11/41 , G11C16/0441
摘要： A memory has first and second storage cells, each with a floating node, that store complementary data values. Interlaced inverters quickly sense a voltage difference between the storage cells and provide a data value output when the memory is read. Each floating node includes a tunneling gate of a tunneling transistor, a gate of a bitline transistor, and a plate of a coupling capacitor.
摘要翻译：存储器具有存储补充数据值的第一和第二存储单元，每个具有浮动节点。隔行逆变器快速检测存储单元之间的电压差，并在读取存储器时提供数据值输出。每个浮动节点包括隧道晶体管的隧道栅极，位线晶体管的栅极和耦合电容器的板。

24. 发明授权

US07567449B2 One-time-programmable logic bit with multiple logic elements 有权
标题翻译：具有多个逻辑元件的一次可编程逻辑位
公开(公告)号：US07567449B2
公开(公告)日：2009-07-28
申请号：US11588775
申请日：2006-10-27
申请人： Sunhom Paak , Hsung Jai Im , Boon Yong Ang
发明人： Sunhom Paak , Hsung Jai Im , Boon Yong Ang
IPC分类号： G11C17/00
CPC分类号： G11C17/18 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.
摘要翻译：具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并提供存储器单元的二进制存储器输出。在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同类型的OTP存储器。

25. 发明授权

US07501879B1 eFuse resistance sensing scheme with improved accuracy 有权
标题翻译： eFuse电阻传感方案具有提高的精度
公开(公告)号：US07501879B1
公开(公告)日：2009-03-10
申请号：US11717836
申请日：2007-03-13
申请人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
发明人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
IPC分类号： G11C17/18 , H01H85/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.
摘要翻译： eFuse感测电路取代了用于提供常规eFuse电路的“读取”输出状态的逆变器。感测电路包括具有耦合到eFuse电路的一个输入和耦合到参考电压发生器电路的第二输入的比较器。参考电压发生器电路包括内部电阻器。提供感测电路的晶体管以模拟eFuse电路的晶体管，使得由于工艺，电压和温度而导致的晶体管的变化将基本相同。然后将感测电路的电阻与比较器的eFuse的电阻进行有效的比较，而与温度和工艺变化无关。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式