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21. 发明授权

US06751721B1 Broadcast invalidate scheme 失效
标题翻译：广播无效方案
公开(公告)号：US06751721B1
公开(公告)日：2004-06-15
申请号：US09652165
申请日：2000-08-31
申请人： David A. J. Webb, Jr. , Richard E. Kessler , Steve Lang , Aaron T. Spink
发明人： David A. J. Webb, Jr. , Richard E. Kessler , Steve Lang , Aaron T. Spink
IPC分类号： G06F1300
CPC分类号： G06F12/0826
摘要： A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster. All processors within the cluster invalidate a local copy of the shared data if it exists and once the master processor receives acknowledgements from all processors in the cluster, the master processor sends an invalidate acknowledgment message to the processor that originally requested the exclusive rights to the shared data. The cache coherency is scalable and may be implemented using the hybrid point-to-point/broadcast scheme or a conventional point-to-point only directory-based invalidate scheme.
摘要翻译：用于分发无效消息以改变计算机系统中的共享数据的状态的基于目录的多处理器高速缓存控制方案。多个处理器被分组成多个簇。目录控制器跟踪发送到集群中的处理器的共享数据的副本。当从处理器接收到请求许可修改数据的共享副本的独占请求时，目录控制器产生无效消息，请求共享相同数据的其他处理器使该数据无效。这些无效消息通过点对点传输仅发送到实际包含数据共享副本的集群中的主处理器。在收到无效消息后，主处理器将有序扇入/扇出进程中的无效消息广播到群集中的每个处理器。集群内的所有处理器使共享数据的本地副本（如果存在）无效，并且一旦主处理器从集群中的所有处理器接收到确认，则主处理器向原始请求共享的专有权的处理器发送无效确认消息数据。高速缓存一致性是可扩展的，并且可以使用混合点对点/广播方案或常规的仅基于点对点的仅基于目录的无效方案来实现。

22. 发明授权

US06678840B1 Fault containment and error recovery in a scalable multiprocessor 有权
标题翻译：可扩展多处理器中的故障控制和错误恢复
公开(公告)号：US06678840B1
公开(公告)日：2004-01-13
申请号：US09651949
申请日：2000-08-31
申请人： Richard E. Kessler , Peter J. Bannon , Kourosh Gharachorloo , Thukalan V. Verghese
发明人： Richard E. Kessler , Peter J. Bannon , Kourosh Gharachorloo , Thukalan V. Verghese
IPC分类号： G06F1100
CPC分类号： G06F11/0793 , G06F11/0724 , G06F15/17
摘要： A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.
摘要翻译：多处理器计算机系统允许实现各种类型的分区以包含和隔离硬件故障。各种类型的分区包括硬，半硬，坚固和软分区。每个分区可以包括一个或多个处理器。当检测到与处理器相关联的故障时，可以切断与系统中的相邻处理器的连接，从而防止损坏的数据污染系统的其余部分。如果处理器间连接被切断，则在其他处理器中的消息备份时，系统中的消息流量可能会变得拥塞。因此，每个处理器包括各种定时器，以监视可能由于切断的连接造成的交通拥堵。而不是让处理器继续等待能够发送其消息，定时器将在预编程的时间段过期，并且处理器将采取适当的动作，例如简单地删除排队的消息，以防止系统锁定。

23. 发明授权

US06636955B1 Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature 失效
标题翻译：同步多个偏斜源同步数据通道与自动初始化功能的机制
公开(公告)号：US06636955B1
公开(公告)日：2003-10-21
申请号：US09652480
申请日：2000-08-31
申请人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
发明人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F13/1689
摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself. Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.
摘要翻译：计算机系统具有存储器控制器，其包括耦合到多个存储器通道的读取缓冲器。存储器控制器有利地消除由存储器模块位于与存储器控制器不同的距离处引起的通道间偏移。存储器控制器优选地包括用于每个存储器通道的通道接口和同步逻辑电路。该电路包括读取和写入缓冲区，读取缓冲区的加载和卸载指针。卸载指针逻辑生成卸载指针，加载指针逻辑生成加载指针。指针优选地是根据两个不同的时钟信号递增的自由运行指针。负载指针根据由存储器控制器产生的时钟增加，但是已经被引出到存储器模块和从存储器模块返回。卸载指针根据计算机系统本身产生的时钟增加。因为每个存储器通道的迹线长度可能不同，所以存储器模块将读数据提供给存储器控制器所花费的时间可能对于每个通道而言可能不同。 “偏斜”被定义为数据到达最早通道时和数据到达最新通道之间的时间差。在系统初始化期间，指针是同步的。初始化之后，这些指针用于加载和卸载读取缓冲区，从而消除内部信道偏移的影响。

24. 发明授权

US06493802B1 Method and apparatus for performing speculative memory fills into a microprocessor 失效
标题翻译：用于执行推测性存储器填充到微处理器的方法和装置
公开(公告)号：US06493802B1
公开(公告)日：2002-12-10
申请号：US09099396
申请日：1998-06-18
申请人： Rahul Razdan , James B. Keller , Richard E. Kessler
发明人： Rahul Razdan , James B. Keller , Richard E. Kessler
IPC分类号： G06F1212
CPC分类号： G06F12/0815 , G06F12/0806 , G06F12/0859 , G06F12/0862 , G06F2212/507
摘要： According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more other versions of the information located in one or more caches. The process of filling the designated cache with the information is started by locating the information in the main memory and locating other versions of the information identified by the address in the caches. The validity of the information located in the main memory is determined after locating the other versions of the information. The process of filling the designated cache with the information located in the main memory is initiated before determining the validity of the information located in main memory. Thus, the memory reference is speculative.
摘要翻译：根据本发明，推测性地填充多处理器系统内的高速缓存。为了推测地填充指定的高速缓存，本发明首先确定识别位于主存储器中的信息的地址。地址还可以标识位于一个或多个高速缓存中的信息的一个或多个其他版本。通过将信息定位在主存储器中并定位在该高速缓存中由该地址识别的信息的其他版本来启动用信息填充指定高速缓存的过程。位于主存储器中的信息的有效性是在查找信息的其他版本之后确定的。在确定位于主存储器中的信息的有效性之前启动用位于主存储器中的信息填充指定高速缓存的过程。因此，内存引用是推测性的。

25. 发明授权

US06349366B1 Method and apparatus for developing multiprocessor cache control protocols using a memory management system generating atomic probe commands and system data control response commands 失效
标题翻译：使用生成原子探测命令和系统数据控制响应命令的存储器管理系统开发多处理器缓存控制协议的方法和装置
公开(公告)号：US06349366B1
公开(公告)日：2002-02-19
申请号：US09099385
申请日：1998-06-18
申请人： Rahul Razdan , James B. Keller , Richard E. Kessler
发明人： Rahul Razdan , James B. Keller , Richard E. Kessler
IPC分类号： G06F1200
CPC分类号： G06F12/0815
摘要： A memory management system couples processors to each other and to a main memory. Each processor may have one or more associated caches local to that processor. A system port of the memory management system receives a request from a source processor of the processors to access a block of data from the main memory. A memory manager of the memory management system then converts the request into a probe command having a data movement part identifying a condition for movement of the block out of a cache of a target processor and a next coherence state part indicating a next state of the block in the cache of the target processor.
摘要翻译：存储器管理系统将处理器彼此耦合到主存储器。每个处理器可以具有该处理器本地的一个或多个相关联的高速缓存。存储器管理系统的系统端口接收来自处理器的源处理器的请求以从主存储器访问数据块。存储器管理系统的存储器管理器然后将该请求转换成具有数据移动部分的探测命令，该数据移动部分标识出用于从目标处理器的高速缓存中移出块的条件，以及指示块的下一个状态的下一个相干状态部分在目标处理器的缓存中。

26. 发明授权

US06216174B1 System and method for fast barrier synchronization 有权
标题翻译：快速屏障同步的系统和方法
公开(公告)号：US06216174B1
公开(公告)日：2001-04-10
申请号：US09162673
申请日：1998-09-29
申请人： Steven L. Scott , Richard E. Kessler
发明人： Steven L. Scott , Richard E. Kessler
IPC分类号： G06F1580
CPC分类号： G06F9/52 , G06F9/522
摘要： Improved method and apparatus for facilitating fast barrier synchronization in a parallel-processing system. A single input signal and a single output signal, and a single bit of state (“barrier_bit”) is added to each processor to support a barrier. The input and output signal are coupled to a dedicated barrier-logic circuit that includes memory-mapped bit-vector registers to track the “participating” processors and the “joined” processors for the barrier. A “bjoin” instruction executed in a processor causes a pulse to be sent on the output signal, which in turn causes that processor's bit in the dedicated barrier-logic circuit's “joined” register to be set. When the “joined” bits for all participating processors (as indicated by the “participating” register) are all set, the “joined” register is cleared, and a pulse is sent to the input signal of all the participating processors, which in turn causes each of those processor's barrier_bit to be set.
摘要翻译：用于促进并行处理系统中的快速屏障同步的改进的方法和装置。单个输入信号和单个输出信号以及单个位状态（“barrier_bit”）被添加到每个处理器以支持屏障。输入和输出信号耦合到专用的屏障逻辑电路，该电路包括存储器映射的位向量寄存器以跟踪“参与”处理器和用于屏障的“连接”处理器。在处理器中执行的“bjoin”指令使得在输出信号上发送脉冲，这又导致专用势垒逻辑电路的“加入”寄存器中的处理器的位被置位。当所有参与处理器（由“参与”寄存器指示）的“加入”位全部被置位时，“已加入”寄存器被清除，并且脉冲被发送到所有参与处理器的输入信号，反过来导致这些处理器的barrier_bit中的每一个被设置。

27. 发明授权

US5583990A System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel 失效
标题翻译：用于在虚拟通道之间分配消息以避免死锁并优化每种类型的虚拟通道上的消息流量的系统
公开(公告)号：US5583990A
公开(公告)日：1996-12-10
申请号：US165266
申请日：1993-12-10
申请人： Mark S. Birrittella , Richard E. Kessler , Steven M. Oberlin , Randal S. Passint , Greg Thorson
发明人： Mark S. Birrittella , Richard E. Kessler , Steven M. Oberlin , Randal S. Passint , Greg Thorson
IPC分类号： F16C39/06 , F16C32/04 , G06F15/16 , G06F15/173 , G06F15/80 , H04L12/56 , G06F13/00
CPC分类号： H04L45/06 , G06F15/17337 , G06F15/17381 , H04L45/10 , H04L49/101 , H04L49/205 , H04L49/251
摘要： A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.
摘要翻译：用于并行处理计算机的多维互连和路由设备将三维结构中的处理元件连接在一起。互连和路由设备包括多个处理单元节点。通信中的至少一个处理元件与主机系统连接。互连网络将处理元件节点连接在X，Y和Z维度上。该网络包括将多个处理元件中的每一个连接到X，Y和Z各维度的正负方向的相邻处理元件的通信路径。

28. 发明授权

US09906468B2 Packet traffic control in a network processor 有权
公开(公告)号：US09906468B2
公开(公告)日：2018-02-27
申请号：US13283252
申请日：2011-10-27
申请人： Richard E. Kessler , Michael Sean Bertone
发明人： Richard E. Kessler , Michael Sean Bertone
IPC分类号： H04L12/933 , H04L12/873
CPC分类号： H04L49/15 , H04L47/52
摘要： A network processor controls packet traffic in a network by maintaining a count of pending packets. In the network processor, a pipe identifier (ID) is assigned to each of a number of paths connecting a packet output to respective network interfaces receiving those packets. A corresponding pipe ID is attached to each packet as it is transmitted. A counter employs the pipe ID to maintain a count of packets to be transmitted by a network interface. As a result, the network processor manages traffic on a per-pipe ID basis to ensure that traffic thresholds are not exceeded.

29. 发明授权

US08977944B2 DRAM address protection 有权
标题翻译： DRAM地址保护
公开(公告)号：US08977944B2
公开(公告)日：2015-03-10
申请号：US13325943
申请日：2011-12-14
申请人： Aseem Maheshwari , Michael S. Bertone , Richard E. Kessler
发明人： Aseem Maheshwari , Michael S. Bertone , Richard E. Kessler
IPC分类号： G06F11/00 , G11C29/00 , G06F11/10 , H03M13/09
CPC分类号： G06F11/1004 , G06F11/1016 , G06F11/1076 , H03M13/09
摘要： In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
摘要翻译：在一个实施例中，系统包括存储器，以及经由地址总线，数据总线和错误代码总线耦合到存储器的存储器控制器。存储器将数据存储在地址处，并在地址处存储错误代码。基于相应数据和地址的函数生成错误代码。

30. 发明授权

US08364851B2 Scalable efficient I/O port protocol 有权
标题翻译：可扩展的高效I / O端口协议
公开(公告)号：US08364851B2
公开(公告)日：2013-01-29
申请号：US10677583
申请日：2003-10-02
申请人： Richard E. Kessler , Samuel H. Duncan , David W. Hartwell , David A. J. Webb, Jr. , Steve Lang
发明人： Richard E. Kessler , Samuel H. Duncan , David W. Hartwell , David A. J. Webb, Jr. , Steve Lang
IPC分类号： G06F3/00
CPC分类号： G06F15/17381 , G06F12/0817 , G06F2212/621
摘要： A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.
摘要翻译：公开了一种支持高性能，可扩展和高效的I / O端口协议来连接到I / O设备的系统。分布式多处理计算机系统包含多个处理器，每个处理器都耦合到实现I / O端口协议的I / O桥ASIC。一个或多个I / O设备耦合到I / O桥ASIC，每个I / O设备能够通过发送和接收消息分组来访问计算机系统中的机器资源。计算机系统中的机器资源包括数据块，寄存器和中断队列。计算机系统中的每个处理器耦合到能够存储处理器之间共享的数据块的存储器模块。使用基于目录的一致性协议来维护该共享存储器系统中的共享数据块的一致性。使用与存储系统相同的一致性协议来维护I / O设备读写访问期间传输的数据块的一致性。只有当I / O桥ASIC具有数据块的排他副本时，I / O桥ASIC才能缓存在I / O设备读或写访问期间传输的数据块。 I / O桥ASIC包括支持数据块的顺序和无序DMA读和写数据流的DMA设备。由DMA设备执行的数据块的顺序读取流总是导致DMA设备接收不必写入存储器模块的相干数据块。

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