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1. 发明授权

US09906468B2 Packet traffic control in a network processor 有权
公开(公告)号：US09906468B2
公开(公告)日：2018-02-27
申请号：US13283252
申请日：2011-10-27
申请人： Richard E. Kessler , Michael Sean Bertone
发明人： Richard E. Kessler , Michael Sean Bertone
IPC分类号： H04L12/933 , H04L12/873
CPC分类号： H04L49/15 , H04L47/52
摘要： A network processor controls packet traffic in a network by maintaining a count of pending packets. In the network processor, a pipe identifier (ID) is assigned to each of a number of paths connecting a packet output to respective network interfaces receiving those packets. A corresponding pipe ID is attached to each packet as it is transmitted. A counter employs the pipe ID to maintain a count of packets to be transmitted by a network interface. As a result, the network processor manages traffic on a per-pipe ID basis to ensure that traffic thresholds are not exceeded.

2. 发明申请

US20130107711A1 PACKET TRAFFIC CONTROL IN A NETWORK PROCESSOR 有权
标题翻译：网络处理器中的分组交通控制
公开(公告)号：US20130107711A1
公开(公告)日：2013-05-02
申请号：US13283252
申请日：2011-10-27
申请人： Richard E. Kessler , Michael Sean Bertone
发明人： Richard E. Kessler , Michael Sean Bertone
IPC分类号： H04L12/26
CPC分类号： H04L49/15 , H04L47/52
摘要： A network processor controls packet traffic in a network by maintaining a count of pending packets. In the network processor, a pipe identifier (ID) is assigned to each of a number of paths connecting a packet output to respective network interfaces receiving those packets. A corresponding pipe ID is attached to each packet as it is transmitted. A counter employs the pipe ID to maintain a count of packets to be transmitted by a network interface. As a result, the network processor manages traffic on a per-pipe ID basis to ensure that traffic thresholds are not exceeded.
摘要翻译：网络处理器通过维持未决分组的计数来控制网络中的分组流量。在网络处理器中，将分组输出连接到接收这些分组的各个网络接口的多个路径中的每一个分配给管道标识符（ID）。相应的管道ID在发送时附加到每个数据包。计数器采用管道ID来维护网络接口要发送的数据包的计数。因此，网络处理器在每个管道ID的基础上管理流量，以确保不超过流量阈值。

3. 发明授权

US09612934B2 Network processor with distributed trace buffers 有权
公开(公告)号：US09612934B2
公开(公告)日：2017-04-04
申请号：US13284289
申请日：2011-10-28
申请人： Bradley D. Dobbie , David H. Asher , Richard E. Kessler
发明人： Bradley D. Dobbie , David H. Asher , Richard E. Kessler
IPC分类号： G06F3/00 , G06F11/34 , G06F13/40 , G06F12/084 , G06F3/16 , G06F1/32 , G06F13/38
CPC分类号： G06F11/3495 , G06F1/3203 , G06F3/16 , G06F11/349 , G06F12/084 , G06F13/385 , G06F13/4022
摘要： A network processor includes a cache and a several groups of processors for accessing the cache. A memory interconnect provides for connecting the processors to the cache via a plurality of memory buses. A number of trace buffers are also connected to the bus and operate to store information regarding commands and data transmitted across the bus. The trace buffers share a common address space, thereby enabling access to the trace buffers as a single entity.

4. 发明授权

US08885480B2 Packet priority in a network processor 有权
标题翻译：网络处理器中的包优先级
公开(公告)号：US08885480B2
公开(公告)日：2014-11-11
申请号：US13277613
申请日：2011-10-20
申请人： Wilson P. Snyder, II , Daniel A. Katz , Richard E. Kessler , Srikanth Gummalla
发明人： Wilson P. Snyder, II , Daniel A. Katz , Richard E. Kessler , Srikanth Gummalla
IPC分类号： H04L1/00 , H04L12/931 , H04L12/825
CPC分类号： H04L49/205 , H04L47/263 , H04L49/505
摘要： In a network processor, a “port-kind” identifier (ID) is assigned to each port. Parsing circuitry employs the port-kind ID to select the configuration information associate with a received packet. The port kind ID can also be stored at a data structure presented to software, along with a larger port number (indicating an interface and/or channel). Based on the port kind ID and extracted information about the packet, a backpressure ID is calculated for the packet. The backpressure ID is implemented to assign a priority to the packet, as well as determine whether a traffic threshold is exceeded, thereby enabling a backpressure signal to limit packet traffic associated with the particular backpressure ID.
摘要翻译：在网络处理器中，为每个端口分配“端口类型”标识符（ID）。解析电路使用端口种类ID来选择与接收到的分组相关联的配置信息。端口种类ID也可以存储在呈现给软件的数据结构以及更大的端口号（指示接口和/或信道）上。根据端口种类ID和关于分组的提取信息，计算分组的背压ID。背压ID被实现以分配分组的优先级，并且确定是否超过流量阈值，从而使背压信号能够限制与特定背压ID相关联的分组流量。

5. 发明授权

US08850125B2 System and method to provide non-coherent access to a coherent memory system 有权
标题翻译：提供对相干存储器系统的非相干访问的系统和方法
公开(公告)号：US08850125B2
公开(公告)日：2014-09-30
申请号：US13280756
申请日：2011-10-25
申请人： Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler , Aseem Maheshwari
发明人： Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler , Aseem Maheshwari
IPC分类号： G06F13/00 , G06F13/28 , G06F12/08
CPC分类号： G06F12/0888 , G06F12/08 , G06F12/0831
摘要： In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
摘要翻译：在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访问路径和到存储器的旁路高速缓存访问路径，接收从旁路高速缓存访问路径上的存储器读取图形数据的请求，以及接收从缓存访问路径上的内存中读取非图形数据的请求。一种方法包括在存储器控制器处接收来自旁路高速缓存访问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访问路径从存储器读取非图形数据，在内存控制器中，在使用仲裁的请求中。

6. 发明申请

US20100023626A1 METHOD AND APPARATUS FOR REDUCING HOST OVERHEAD IN A SOCKET SERVER IMPLEMENTATION 有权
标题翻译：用于减少插座服务器实现中的主机的方法和装置
公开(公告)号：US20100023626A1
公开(公告)日：2010-01-28
申请号：US12574263
申请日：2009-10-06
申请人： Muhammad R. Hussain , Richard E. Kessler , Faisal Masood , Robert A. Sanzone , Imran Badr
发明人： Muhammad R. Hussain , Richard E. Kessler , Faisal Masood , Robert A. Sanzone , Imran Badr
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9063 , H04L69/162 , H04L69/163 , H04L69/165
摘要： A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the network services processor and the application buffers. After the transfer, a completion notification is written to one of the two control queues in the host system. The completion notification includes the size of the data transferred and an identifier associated with the socket. The identifier identifies a thread associated with the transferred data and the location of the data in the host system.
摘要翻译：在主机系统上执行的网络应用程序将存储在队列中的主机存储器中的应用缓冲器列表提供给耦合到主机系统的网络服务处理器。应用程序缓冲区用于存储在网络应用程序和在远程主机系统中执行的远程网络应用程序之间建立的套接字上传输的数据。使用应用缓冲器，由网络服务处理器通过网络接收的数据在网络服务处理器和应用缓冲器之间传送。在传输之后，将完成通知写入主机系统中的两个控制队列之一。完成通知包括传输的数据的大小和与套接字相关联的标识符。标识符标识与传送的数据相关联的线程和主机系统中数据的位置。

7. 发明授权

US07594081B2 Direct access to low-latency memory 有权
标题翻译：直接访问低延迟内存
公开(公告)号：US07594081B2
公开(公告)日：2009-09-22
申请号：US11024002
申请日：2004-12-28
申请人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
发明人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3824 , G06F9/3885 , G06F12/0888
摘要： A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.
摘要翻译：提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。非普通的加载/存储指令可以是协处理器指令。存储器可以是低延迟型存储器。处理器可以包括多个处理器核。

8. 发明授权

US07558925B2 Selective replication of data structures 有权
标题翻译：数据结构的选择性复制
公开(公告)号：US07558925B2
公开(公告)日：2009-07-07
申请号：US11335189
申请日：2006-01-18
申请人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler
发明人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler
IPC分类号： G06F12/02
CPC分类号： G06F12/06 , G06F12/0653 , G06F2212/174
摘要： Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).
摘要翻译：提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。存储器包括被配置为存储相同数据结构的复制副本的多个单独存储体。在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和与它们被存储（即，写入）相比更加加载（即读）的其他数据结构。

9. 发明授权

US07024533B2 Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature 失效
公开(公告)号：US07024533B2
公开(公告)日：2006-04-04
申请号：US10441451
申请日：2003-05-20
申请人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
发明人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

10. 发明授权

US06751721B1 Broadcast invalidate scheme 失效
标题翻译：广播无效方案
公开(公告)号：US06751721B1
公开(公告)日：2004-06-15
申请号：US09652165
申请日：2000-08-31
申请人： David A. J. Webb, Jr. , Richard E. Kessler , Steve Lang , Aaron T. Spink
发明人： David A. J. Webb, Jr. , Richard E. Kessler , Steve Lang , Aaron T. Spink
IPC分类号： G06F1300
CPC分类号： G06F12/0826
摘要： A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster. All processors within the cluster invalidate a local copy of the shared data if it exists and once the master processor receives acknowledgements from all processors in the cluster, the master processor sends an invalidate acknowledgment message to the processor that originally requested the exclusive rights to the shared data. The cache coherency is scalable and may be implemented using the hybrid point-to-point/broadcast scheme or a conventional point-to-point only directory-based invalidate scheme.
摘要翻译：用于分发无效消息以改变计算机系统中的共享数据的状态的基于目录的多处理器高速缓存控制方案。多个处理器被分组成多个簇。目录控制器跟踪发送到集群中的处理器的共享数据的副本。当从处理器接收到请求许可修改数据的共享副本的独占请求时，目录控制器产生无效消息，请求共享相同数据的其他处理器使该数据无效。这些无效消息通过点对点传输仅发送到实际包含数据共享副本的集群中的主处理器。在收到无效消息后，主处理器将有序扇入/扇出进程中的无效消息广播到群集中的每个处理器。集群内的所有处理器使共享数据的本地副本（如果存在）无效，并且一旦主处理器从集群中的所有处理器接收到确认，则主处理器向原始请求共享的专有权的处理器发送无效确认消息数据。高速缓存一致性是可扩展的，并且可以使用混合点对点/广播方案或常规的仅基于点对点的仅基于目录的无效方案来实现。

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