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1. 发明授权

US08977944B2 DRAM address protection 有权
标题翻译： DRAM地址保护
公开(公告)号：US08977944B2
公开(公告)日：2015-03-10
申请号：US13325943
申请日：2011-12-14
申请人： Aseem Maheshwari , Michael S. Bertone , Richard E. Kessler
发明人： Aseem Maheshwari , Michael S. Bertone , Richard E. Kessler
IPC分类号： G06F11/00 , G11C29/00 , G06F11/10 , H03M13/09
CPC分类号： G06F11/1004 , G06F11/1016 , G06F11/1076 , H03M13/09
摘要： In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
摘要翻译：在一个实施例中，系统包括存储器，以及经由地址总线，数据总线和错误代码总线耦合到存储器的存储器控制器。存储器将数据存储在地址处，并在地址处存储错误代码。基于相应数据和地址的函数生成错误代码。

2. 发明申请

US20120185752A1 DRAM ADDRESS PROTECTION 有权
标题翻译： DRAM地址保护
公开(公告)号：US20120185752A1
公开(公告)日：2012-07-19
申请号：US13325943
申请日：2011-12-14
申请人： Aseem Maheshwari , Michael S. Bertone , Richard E. Kessler
发明人： Aseem Maheshwari , Michael S. Bertone , Richard E. Kessler
IPC分类号： H03M13/09 , G06F11/10 , H03M13/05
CPC分类号： G06F11/1004 , G06F11/1016 , G06F11/1076 , H03M13/09
摘要： In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
摘要翻译：在一个实施例中，系统包括存储器，以及经由地址总线，数据总线和错误代码总线耦合到存储器的存储器控制器。存储器将数据存储在地址处，并在地址处存储错误代码。基于相应数据和地址的函数生成错误代码。

3. 发明授权

US08850125B2 System and method to provide non-coherent access to a coherent memory system 有权
标题翻译：提供对相干存储器系统的非相干访问的系统和方法
公开(公告)号：US08850125B2
公开(公告)日：2014-09-30
申请号：US13280756
申请日：2011-10-25
申请人： Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler , Aseem Maheshwari
发明人： Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler , Aseem Maheshwari
IPC分类号： G06F13/00 , G06F13/28 , G06F12/08
CPC分类号： G06F12/0888 , G06F12/08 , G06F12/0831
摘要： In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
摘要翻译：在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访问路径和到存储器的旁路高速缓存访问路径，接收从旁路高速缓存访问路径上的存储器读取图形数据的请求，以及接收从缓存访问路径上的内存中读取非图形数据的请求。一种方法包括在存储器控制器处接收来自旁路高速缓存访问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访问路径从存储器读取非图形数据，在内存控制器中，在使用仲裁的请求中。

4. 发明授权

US09465662B2 Processor with efficient work queuing 有权
标题翻译：处理器具有高效的工作排队
公开(公告)号：US09465662B2
公开(公告)日：2016-10-11
申请号：US13274767
申请日：2011-10-17
申请人： Richard E. Kessler , Aseem Maheshwari , Robert Sanzone
发明人： Richard E. Kessler , Aseem Maheshwari , Robert Sanzone
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48
CPC分类号： G06F9/5027 , G06F9/4881 , G06F2209/509
摘要： Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor.
摘要翻译：提交给协处理器的工作通过多个输入队列之一进入，用于提供各种服务质量水平。内存链接列表存储由网络服务处理器执行的工作，以响应网络服务处理器中的处理资源的缺乏。响应于网络服务处理器中的处理资源的可用性，将工作从内存中墨迹列表移回到网络服务处理器。

5. 发明申请

US20130097608A1 Processor With Efficient Work Queuing 有权
标题翻译：处理器有效的工作排队
公开(公告)号：US20130097608A1
公开(公告)日：2013-04-18
申请号：US13274767
申请日：2011-10-17
申请人： Richard E. Kessler , Aseem Maheshwari , Robert Sanzone
发明人： Richard E. Kessler , Aseem Maheshwari , Robert Sanzone
IPC分类号： G06F9/46
CPC分类号： G06F9/5027 , G06F9/4881 , G06F2209/509
摘要： Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor.
摘要翻译：提交给协处理器的工作通过多个输入队列之一进入，用于提供各种服务质量水平。内存链接列表存储由网络服务处理器执行的工作，以响应网络服务处理器中的处理资源的缺乏。响应于网络服务处理器中的处理资源的可用性，将工作从内存中墨迹列表移回到网络服务处理器。

6. 发明申请

US20130103909A1 SYSTEM AND METHOD TO PROVIDE NON-COHERENT ACCESS TO A COHERENT MEMORY SYSTEM 有权
标题翻译：提供对相关存储器系统的非相互访问的系统和方法
公开(公告)号：US20130103909A1
公开(公告)日：2013-04-25
申请号：US13280756
申请日：2011-10-25
申请人： Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler , Aseem Maheshwari
发明人： Jeffrey Pangborn , Gregg A. Bouchard , Rajan Goyal , Richard E. Kessler , Aseem Maheshwari
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/08 , G06F12/0831
摘要： In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
摘要翻译：在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访问路径和到存储器的旁路高速缓存访问路径，接收从旁路高速缓存访问路径上的存储器读取图形数据的请求，以及接收从缓存访问路径上的内存中读取非图形数据的请求。一种方法包括在存储器控制器处接收来自旁路高速缓存访问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访问路径从存储器读取非图形数据，在内存控制器中，在使用仲裁的请求中。

7. 发明授权

US06754739B1 Computer resource management and allocation system 有权
标题翻译：计算机资源管理与分配系统
公开(公告)号：US06754739B1
公开(公告)日：2004-06-22
申请号：US09651945
申请日：2000-08-31
申请人： Richard E. Kessler , Michael S. Bertone , Gregg A. Bouchard , Maurice B. Steinman
发明人： Richard E. Kessler , Michael S. Bertone , Gregg A. Bouchard , Maurice B. Steinman
IPC分类号： G06F1300
CPC分类号： G06F9/544
摘要： A method and architecture for improved system resource management and allocation for the processing of request and response messages in a computer system. The resource management scheme provides for dynamically sharing system resources, such as data buffers, between request and response messages or transactions. In particular, instead of simply dedicating a portion of the system resources to requests and the remaining portion to responses, a minimum amount of resources are reserved for responses and a minimum amount for requests, while the remaining resources are dynamically shared between both types of messages. The method and architecture of the present invention allows for more efficient use of system resources, while avoiding deadlock conditions and ensuring a minimum service rate for requests.
摘要翻译：一种用于改进系统资源管理和分配以在计算机系统中处理请求和响应消息的方法和架构。资源管理方案提供在请求和响应消息或事务之间动态共享系统资源，例如数据缓冲器。特别地，不是简单地将系统资源的一部分专用于请求，而将余下的部分用于响应，而是为响应保留最小量的资源和用于请求的最小量，而剩余的资源在两种类型的消息之间动态共享。本发明的方法和体系结构允许更有效地利用系统资源，同时避免死锁状况并确保请求的最低服务速率。

8. 发明授权

US09596193B2 Messaging with flexible transmit ordering 有权
标题翻译：消息传递灵活的发送顺序
公开(公告)号：US09596193B2
公开(公告)日：2017-03-14
申请号：US13326091
申请日：2011-12-14
申请人： Richard E. Kessler , Thomas F. Hummel , Robert A. Sanzone , Daniel A. Katz , Michael S. Bertone
发明人： Richard E. Kessler , Thomas F. Hummel , Robert A. Sanzone , Daniel A. Katz , Michael S. Bertone
IPC分类号： H04L12/56 , H04L12/861 , H04L12/935 , H04L12/939 , H04L12/741 , H04L29/06
CPC分类号： H04L49/9057 , H04L45/74 , H04L49/3072 , H04L49/552 , H04L69/22
摘要： In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.
摘要翻译：在一个实施例中，系统包括分组接收单元。分组接收单元被配置为接收分组，创建指示多个核中的分组的调度的报头，并且连接报头和分组。标题是基于数据包的内容。在一个实施例中，系统包括被配置为存储分组的多个片段的发射仓，所述片段已经被发送到目的地，并且发送仓已经没有收到来自目的地的片段接收的确认。该系统还包括与发射仓连接的限制验证器。限制验证器被配置为接收片段并且确定片段是否可以被发送并存储在传送仓中。

9. 发明申请

US20120155474A1 MESSAGING WITH FLEXIBLE TRANSMIT ORDERING 有权
标题翻译：使用灵活的发送订单进行消息传递
公开(公告)号：US20120155474A1
公开(公告)日：2012-06-21
申请号：US13326091
申请日：2011-12-14
申请人： Richard E. Kessler , Thomas F. Hummel , Robert A. Sanzone , Daniel A. Katz , Michael S. Bertone
发明人： Richard E. Kessler , Thomas F. Hummel , Robert A. Sanzone , Daniel A. Katz , Michael S. Bertone
IPC分类号： H04L12/56
CPC分类号： H04L49/9057 , H04L45/74 , H04L49/3072 , H04L49/552 , H04L69/22
摘要： In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.
摘要翻译：在一个实施例中，系统包括分组接收单元。分组接收单元被配置为接收分组，创建指示多个核中的分组的调度的报头，并且连接报头和分组。标题是基于数据包的内容。在一个实施例中，系统包括被配置为存储分组的多个片段的发射仓，所述片段已经被发送到目的地，并且发送仓已经没有收到来自目的地的片段接收的确认。该系统还包括与发射仓连接的限制验证器。限制验证器被配置为接收片段并且确定片段是否可以被发送并存储在传送仓中。

10. 发明授权

US06662265B1 Mechanism to track all open pages in a DRAM memory system 有权
标题翻译：跟踪DRAM存储器系统中所有打开的页面的机制
公开(公告)号：US06662265B1
公开(公告)日：2003-12-09
申请号：US09652704
申请日：2000-08-31
申请人： Richard E. Kessler , Maurice B. Steinman , Michael S. Bertone , Peter J. Bannon , Gregg A. Bouchard
发明人： Richard E. Kessler , Maurice B. Steinman , Michael S. Bertone , Peter J. Bannon , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A system and method is disclosed to track a large number of open pages in a computer memory system. The computer system contains one or more processors each including a memory controller containing a page table, the page table organized into a plurality of rows with each row able to store an address of an open memory page. A RIMM module containing RDRAM devices is coupled to each processor, each RDRAM containing a plurality of memory banks. The page table increases system memory performance by tracking a large number of open memory pages. Associated with the page table is a bank active table that indicates the memory banks in each RDRAM device having open memory pages. The page table enqueues accesses to the RIMM module in a precharge queue resulting from a page miss caused by the address of an open memory page occupying the same row of the page table as the address of the system memory access resulting in the page miss. The page table also enqueues accesses to system memory in a Row-address-select (“RAS”) queue resulting from a page miss caused by a row of the page table not containing any open memory page address. The page table enqueues accesses to system memory resulting in page hits to open memory pages in a Column-address-select (“CAS”) queue. An entry in the precharge queue is then enqueued into the RAS queue. An entry in the RAS queue after completion is enqueued into the CAS Read or CAS Write queue.
摘要翻译：公开了一种在计算机存储器系统中跟踪大量打开页面的系统和方法。计算机系统包含一个或多个处理器，每个处理器包括包含页表的存储器控制器，所述页表被组织成多行，每行能够存储打开存储器页的地址。包含RDRAM设备的RIMM模块耦合到每个处理器，每个RDRAM包含多个存储器组。页面表通过跟踪大量的开放内存页面来增加系统内存性能。与页表相关联的是一个存储区活动表，指示每个具有打开存储器页的RDRAM设备中的存储体。页表格排队访问预充电队列中的RIMM模块，这是由于打开的内存页面的地址与页表的同一行的地址导致的页错误导致的系统内存访问的地址导致页错过。页表还对由行页地址选择（“RAS”）队列访问系统内存进行排队，这是由于不包含任何打开的内存页地址的页表的行引起的页错误导致的。页面表格对对系统内存的访问进行排队，导致页面命中，以打开列地址选择（“CAS”）队列中的内存页面。然后将预充电队列中的条目排入RAS队列。完成后RAS队列中的条目排入CAS读取或CAS写入队列。

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