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21. 发明授权

US08330254B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08330254B2
公开(公告)日：2012-12-11
申请号：US12647639
申请日：2009-12-28
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
IPC分类号： H01L23/544
CPC分类号： H01L23/48 , G01R31/2884 , G01R31/3025 , G01R31/31721 , H01L22/32 , H01L23/50 , H01L23/5286 , H01L23/544 , H01L24/06 , H01L2223/5446 , H01L2924/01029
摘要： A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.
摘要翻译：一种半导体器件包括其半导体芯片形成区域和位于半导体芯片形成区域之间的划线区域形成的半导体晶片，设置在半导体晶片上的多个半导体芯片电路部分，设置在每个半导体芯片形成区域中的多个第一导电层电连接到每个电路部分的半导体芯片形成区域以及跨越划线区域的一部分将第一导电层彼此电连接的第一连接部分。外部电源或接地焊盘连接到第一导电层和第一连接部分中的任一个。半导体器件包括连接到电路部分的通信部分，其通过电容耦合或电感耦合与外部进行通信。

22. 发明申请

US20120025790A1 ELECTRONIC CIRCUIT, CIRCUIT APPARATUS, TEST SYSTEM, CONTROL METHOD OF THE ELECTRONIC CIRCUIT 审中-公开
标题翻译：电子电路，电路设备，测试系统，电子电路控制方法
公开(公告)号：US20120025790A1
公开(公告)日：2012-02-02
申请号：US13146806
申请日：2010-02-09
申请人： Koichiro Noguchi , Koichi Nose , Yoshihiro Nakagawa , Masayuki Mizuno
发明人： Koichiro Noguchi , Koichi Nose , Yoshihiro Nakagawa , Masayuki Mizuno
IPC分类号： G05F1/10
CPC分类号： G01R31/31721 , G05F1/607
摘要： An electronic circuit includes: a first power line capable of supplying power; a second power line capable of supplying power independently from the first power line; a main circuit connected to the second power line; a detector that detects the supply of power from the first power line or the second power line; and a controller connected to the first power line and the second power line, wherein the controller controls a voltage or a current supplied from the first power line and supplies the voltage or the current to the main circuit when the detector detects supply of power from the first power line.
摘要翻译：电子电路包括：能够供电的第一电力线; 能够独立于所述第一电力线供电的第二电力线; 连接到第二电力线的主电路; 检测器，其检测来自所述第一电力线或所述第二电力线的电力供应; 以及连接到所述第一电力线和所述第二电力线的控制器，其中，所述控制器控制从所述第一电力线提供的电压或电流，并且当所述检测器检测到来自所述主电路的电力供应时，将电压或电流提供给所述主电路第一条电力线。

23. 发明申请

US20110260747A1 SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME 失效
标题翻译：半导体器件及其测试方法
公开(公告)号：US20110260747A1
公开(公告)日：2011-10-27
申请号：US13139609
申请日：2009-12-22
申请人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
发明人： Yoshio Kameda , Yoshihiro Nakagawa , Koichiro Noguchi , Masayuki Mizuno , Koichi Nose
IPC分类号： G01R31/26 , G05F1/10
CPC分类号： G01R31/2884 , G01R31/3012
摘要： A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).
摘要翻译：半导体器件（1）包括其上形成有多个半导体芯片形成区域（1A）的半导体晶片（11），设置在所述半导体芯片形成区域（1A）的每一个内的电路部分（12）半导体晶片（11），设置在每个半导体芯片形成区域（1A）内并连接到电路部分（12））的控制电路部分（14），其控制供应到电路部分（12）的电力，连接到多个控制电路部分（14）的电源线（18）和连接到多个控制电路部分（14）的参考电力线（17）。在每个控制电路部分（14）中，基于来自参考电力线（17）的参考电压来控制从电源线（18）供应的电力的电压。

24. 发明授权

US08023832B2 Light receiving circuit and digital system 有权
标题翻译：光接收电路和数字系统
公开(公告)号：US08023832B2
公开(公告)日：2011-09-20
申请号：US12067625
申请日：2006-09-26
申请人： Masayuki Mizuno , Keishi Ohashi , Koichi Nose , Kenichi Nishi
发明人： Masayuki Mizuno , Keishi Ohashi , Koichi Nose , Kenichi Nishi
IPC分类号： H04B10/06
CPC分类号： H04B10/69 , H03K17/785
摘要： A light receiving circuit (114) includes a light inputting circuit (113) which converts one-system optical signal to be outputted from an optical transmission path (101) to an electrical signal and inverts a potential of the electrical signal each time the optical signal is detected, and a buffer circuit (110) which amplifies the electrical signal converted by the light inputting circuit and outputs the same. According to such configuration, since one-system optical signal may be inputted to the light receiving circuit, a system circuit configuration can be avoided to be complicated.
摘要翻译：光接收电路（114）包括光输入电路（113），其将从光传输路径（101）输出的单系统光信号转换为电信号，并且每当光信号以及缓冲电路（110），放大由光输入电路转换的电信号并输出。根据这样的结构，由于可以将单一系统光信号输入到光接收电路，所以可以避免系统电路结构复杂化。

25. 发明授权

US07821249B2 Phase difference measuring device and phase comparison circuit adjusting method 失效
标题翻译：相位差测量装置及相位比较电路调整方法
公开(公告)号：US07821249B2
公开(公告)日：2010-10-26
申请号：US12088180
申请日：2006-09-28
申请人： Koichi Nose , Masayuki Mizuno
发明人： Koichi Nose , Masayuki Mizuno
IPC分类号： G01R29/26 , G01R27/04
CPC分类号： G01R25/00 , G01R25/04 , H03K5/133 , H03K5/15013
摘要： A phase difference measuring device according to this invention has an object of shortening the measuring time, and includes a plurality of phase difference measuring circuits (104, 105, 106) formed in a row, and phase difference conversion circuits (101, 102, 103) each connected between adjacent phase difference measuring circuits. The phase difference measuring circuit receives first and second signals, respectively gives the first and second signals first and second delay amounts cumulatively a plurality of number of times, and, whenever giving the delay amounts, compares the phases of the first and second signals given the delay amounts, thereby determining which one of the phases leads the other. The phase difference conversion circuit receives the first and second signals input to the phase difference measuring circuit in the preceding stage, respectively gives the first and second signals a first total delay amount (Tr1) as a total of the first delay amounts and a second total delay amount (Ts1) as a total of the second delay amounts given by the phase difference measuring circuit in the preceding stage, and outputs the first and second signals to the phase difference measuring circuit in the succeeding stage.
摘要翻译：根据本发明的相位差测量装置具有缩短测量时间的目的，并且包括形成在一行中的多个相位差测量电路（104,105,106）和相位差转换电路（101,102,103 ）各自连接在相邻的相位差测量电路之间。相位差测量电路接收第一和第二信号，分别给予第一和第二信号第一和第二延迟量多次，并且每当给出延迟量时，给出给定的第一和第二信号的相位延迟量，从而确定哪一个相引导另一个相。相位差转换电路在前一级接收输入到相位差测量电路的第一和第二信号，分别给予第一和第二信号第一总延迟量（Tr1）作为第一延迟量的总和和第二总数延迟量（Ts1）作为前级中的相位差测量电路给出的第二延迟量的总和，并将第一和第二信号输出到后级的相位差测量电路。

26. 发明申请

US20100094577A1 SIGNAL QUALITY MEASUREMENT DEVICE, SPECTRUM MEASUREMENT CIRCUIT, AND PROGRAM 失效
标题翻译：信号质量测量设备，频谱测量电路和程序
公开(公告)号：US20100094577A1
公开(公告)日：2010-04-15
申请号：US12522243
申请日：2007-12-18
申请人： Koichi Nose , Masayuki Mizuno
发明人： Koichi Nose , Masayuki Mizuno
IPC分类号： G01R23/16 , G06F19/00
CPC分类号： H04B17/318 , G01R23/16 , H04B17/15
摘要： Spectrum measurement circuit (101) includes: N- (where N is integer equal or greater than 2) phase clock generation circuit (304) for supplying phase-modulated signals in which the phase of a clock signal is shifted by a phase modulation amount each time the settings of the phase modulation amount are switched; mixer circuit (303) for taking the product of a measured signal supplied from a transmitter and the phase-modulated signals supplied from N-phase clock generation circuit (304); average value output circuit (305) for supplying an average voltage value of the output signal of mixer circuit (303); memory (307) for storing the average voltage value supplied from average value output circuit (305) for each phase modulation amount of the N-phase clock generation circuit (304); and arithmetic unit (308) for using the average voltage value for each phase modulation amount of N-phase clock generation circuit (304) to calculate the signal strength of the measured signal.
摘要翻译：频谱测量电路（101）包括：N个（其中N是等于或大于2的整数）相位时钟产生电路（304），用于提供相位调制信号，其中时钟信号的相位每相位调制量偏移时间相位调制量的设置被切换; 用于获取从发射机提供的测量信号的乘积和从N相时钟产生电路（304）提供的相位调制信号的混频器电路（303）; 平均值输出电路（305），用于提供混频电路（303）的输出信号的平均电压值; 存储器（307），用于存储从N相时钟发生电路（304）的每个相位调制量的平均值输出电路（305）提供的平均电压值; 和运算单元（308），用于使用N相时钟产生电路（304）的每个相位调制量的平均电压值来计算测量信号的信号强度。

27. 发明申请

US20090243624A1 SIGNAL MEASURING DEVICE 失效
标题翻译：信号测量装置
公开(公告)号：US20090243624A1
公开(公告)日：2009-10-01
申请号：US12088352
申请日：2006-09-28
申请人： Koichi Nose , Masayuki Mizuno
发明人： Koichi Nose , Masayuki Mizuno
IPC分类号： G01R31/319
CPC分类号： G01R31/31708
摘要： Small-scale measuring circuits (111-1qum) are arranged in m columns×q rows. The small-scale measuring circuits of each row (111-11m, 121-12m, 1q1-1qm) are connected in series. The respective rows are connected in parallel. Supplying reference signals B having different parameter values to the small-scale measuring circuits (111-11m, . . . ) connected in series makes it possible to improve the measurement range or measurement resolution. Supplying reference signals B having the same parameter to the respective rows can reduce a noise component depending on the transistor size. According to this invention, using a plurality of small-scale measuring circuits in accordance with required measurement performance concerning a measurement range, resolution, noise reduction, or the like can implement the desired performance while minimizing the area of each measuring circuit.
摘要翻译：小规模测量电路（111-1qum）以m列xq行排列。每行的小尺度测量电路（111-11m，121-12m，1q1-1qm）串联连接。相应的行并联连接。将具有不同参数值的参考信号B提供给串联连接的小尺度测量电路（111-11m ...）可以提高测量范围或测量分辨率。向相应行提供具有相同参数的参考信号B可以根据晶体管尺寸减小噪声分量。根据本发明，根据关于测量范围，分辨率，降噪等的所需测量性能来使用多个小规模测量电路可以在最小化每个测量电路的面积的同时实现期望的性能。

28. 发明申请

US20080018372A1 Clock Generating Circuit and Clock Generating Method 失效
标题翻译：时钟发生电路和时钟发生方法
公开(公告)号：US20080018372A1
公开(公告)日：2008-01-24
申请号：US11575168
申请日：2005-09-16
申请人： Koichi Nose , Masayuki Mizuno , Atsufumi Shibayama
发明人： Koichi Nose , Masayuki Mizuno , Atsufumi Shibayama
IPC分类号： H03H11/16
CPC分类号： H03K5/00006 , G06F1/06 , H03K5/13 , H03K5/1565 , H03K2005/00052 , H03L7/07 , H03L7/0814
摘要： A clock converting circuit (1) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit (2) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit (1) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit (1), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.
摘要翻译：时钟转换电路（1）接收并且将具有1 /（fxm）相位差的频率f的m相时钟转换成具有1 /（fxn）相位差的频率f的n相时钟。单相时钟发生电路（2）接收具有1 /（fxn）的相位差等效时间的频率f的n相时钟，以产生与n频率的上升沿或下降沿同步的单相时钟。相位时钟。由于输入到时钟转换电路（1）的m相时钟的频率为'f'，所以如果确定了单相时钟的期望频率，则可以从下列公式得到'n'：频率单相时钟等于（fxn）。该值“n”被设置为时钟转换电路（1），从而从频率f的m相时钟获得频率f的n相时钟，以提供期望频率的单相时钟。

29. 发明授权

US4122688A Refrigerating system 失效
标题翻译：制冷系统
公开(公告)号：US4122688A
公开(公告)日：1978-10-31
申请号：US816938
申请日：1977-07-19
申请人： Taketoshi Mochizuki , Fumio Harada , Tadahiro Imaizumi , Koichi Nose
发明人： Taketoshi Mochizuki , Fumio Harada , Tadahiro Imaizumi , Koichi Nose
IPC分类号： F25B5/02 , F25B47/02 , F25B41/00 , F25B47/00
CPC分类号： F25B5/02 , F25B47/022 , F25B2400/13 , F25B2400/22 , F25B2400/23 , F25B2600/2509
摘要： A refrigerating system having, arranged to form a closed circuit, a refrigerant compressor, a condensor, a receiver and a plurality of sets of evaporators and expansion valves with all the sets connected in parallel with one another. The system further includes a throttle mounted in the circuit between the condenser and the receiver, a branch line and change-over valves for selectively connecting the circuit on the delivery side of the compressor to each evaporator and a passage connecting each evaporator to the receiver by bypassing the associated expansion valve, so that the refrigerantin the state of a compressed gas can be supplied to a desired evaporator to defrost the same and the refrigerant condensed in the defrosted evaporator can be returned to the receiver. The system further includes a bypass line having a throttle, connecting a gas compartment in the upper portion of the receiver to a line on the suction side of the compressor, for returning to the line on the suction side of the compressor, flash gas incorporated in the liquid refrigerant returned from the defrosted evaporator to the receiver.
摘要翻译：具有被设置为形成闭路的制冷系统，制冷剂压缩机，冷凝器，接收器和多组蒸发器和膨胀阀，其中所有组彼此并联连接。该系统还包括安装在冷凝器和接收器之间的电路中的节气门，用于选择性地将压缩机的输出侧上的电路连接到每个蒸发器的分支管线和换向阀以及通过将每个蒸发器连接到接收器的通道绕过相关联的膨胀阀，使得可将压缩气体状态的制冷剂供给到所需的蒸发器以使其除霜，并且在除霜蒸发器中冷凝的制冷剂可以返回到接收器。该系统还包括具有节气门的旁通管线，将接收器上部的气室与压缩机的吸入侧的管路连接，以便返回到压缩机的吸入侧的管线，液体制冷剂从解冻蒸发器返回到接收器。

30. 发明授权

US09187814B2 Hot-dip aluminum alloy plated steel having excellent shear cut edge corrosion resistance and processed part corrosion resistance, and method of manufacturing the same 有权
标题翻译：具有优异的剪切边缘耐腐蚀性和加工部件耐腐蚀性的热浸镀铝合金钢及其制造方法
公开(公告)号：US09187814B2
公开(公告)日：2015-11-17
申请号：US13575072
申请日：2011-05-31
申请人： Koichi Nose , Yasuhide Morimoto , Kohei Tokuda
发明人： Koichi Nose , Yasuhide Morimoto , Kohei Tokuda
IPC分类号： B32B15/01 , B05D1/18 , C23C2/28 , C23C30/00 , C23C2/12 , B32B15/18 , C23C2/04 , B05D3/02 , C22C21/00 , C22C30/00 , C22C38/00 , C22C38/02 , C22C38/06
CPC分类号： C23C2/12 , B05D1/18 , B05D3/02 , B05D3/0254 , B32B15/012 , B32B15/18 , C22C21/00 , C22C30/00 , C22C38/002 , C22C38/005 , C22C38/02 , C22C38/06 , C23C2/04 , C23C2/28 , C23C2/285 , C23C30/00 , C23C30/005 , Y10T428/12569 , Y10T428/12757 , Y10T428/12958 , Y10T428/12972 , Y10T428/12979
摘要： The hot-dip aluminum alloy plated steel has a base steel and a plated layer, in which the composition of the plated layer contains, by % by mass, Fe: 25% to 75%, Mg: 2% to 20%, and Ca: 0.02% to 2% with a remainder of Al and inevitable impurities, the plated layer contains one or both of an α-Mg phase and an Al3Mg2 phase, and the sum of the partial volume fraction of the α-Mg phase and the partial volume fraction of the Al3Mg2 phase in a range of a depth of 5 μm from a surface of the plated layer is 1% to 40%.
摘要翻译：所述热浸镀铝合金钢具有基础钢和镀层，镀层的组成按质量％计含有Fe：25〜75％，Mg：2〜20％，Ca：：0.02％〜2％，余量为Al和不可避免的杂质，镀层含有α-Mg相和Al3Mg2相中的一种或两种，α-Mg相的部分体积分数与部分在镀层表面5μm深度范围内的Al3Mg2相的体积分率为1％〜40％。

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