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21. 发明申请

US20130148406A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD FOR THE SAME 有权
标题翻译：非易失性半导体存储器件及其读取方法
公开(公告)号：US20130148406A1
公开(公告)日：2013-06-13
申请号：US13700329
申请日：2012-07-11
申请人： Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
发明人： Kazuhiko Shimakawa , Kiyotaka Tsuji , Ryotaro Azuma
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/14 , G11C11/1673 , G11C13/0004 , G11C2013/0054 , G11C2213/71 , G11C2213/72 , G11C2213/73 , G11C2213/77
摘要： A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.
摘要翻译：提供一种能够抑制潜流引起的对存储元件的电阻值的检测灵敏度的降低的交叉点非易失性存储装置。该设备包括垂直位和字线; 交叉点单元阵列，其包括存储单元，每个存储单元具有电阻值，该电阻值根据电信号在至少两个电阻状态之间可逆地改变;布置在字和位线的交叉点上; 偏移检测单元阵列，包括在高电阻状态下具有高于存储单元的电阻的偏移检测单元，所述字线由偏移检测单元阵列共享; 读取电路（读出放大器），其基于通过所选位线的电流确定所选存储单元的电阻状态; 以及在读取操作时段中向偏移检测单元阵列提供电流的电流源。

22. 发明授权

US08325508B2 Writing method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储元件和可变电阻非易失性存储器件的写入方法
公开(公告)号：US08325508B2
公开(公告)日：2012-12-04
申请号：US13001905
申请日：2010-06-08
申请人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
发明人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/56 , G11C2213/79
摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).
摘要翻译：提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有最大电阻值。在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻元件从低电阻状态（S52）到高电阻状态（S53）。

23. 发明授权

US08094485B2 Variable resistance nonvolatile storage device with oxygen-deficient oxide layer and asymmetric substrate bias effect 有权
标题翻译：具有氧缺陷氧化层的可变电阻非易失性存储器件和不对称衬底偏置效应
公开(公告)号：US08094485B2
公开(公告)日：2012-01-10
申请号：US12676933
申请日：2008-12-15
申请人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
发明人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt
摘要翻译：可变电阻非易失性存储装置包括通过串联连接可变电阻元件（309）形成的存储单元（300），该可变电阻元件（309）包括基于各自具有不同极性的电信号可逆地改变的可变电阻层（309b）和晶体管（307），包括半导体衬底（301）和两个N型扩散层区域（302a，302b），其中可变电阻层（309b）包括过渡金属的氧缺乏氧化物，下电极和上电极（309a， 309c）的材料由下部电极（309a）的标准电极电位V1，上部电极（309c）的标准电极电位V2，过渡金属的标准电极电位Vt满足Vt

24. 发明授权

US08675387B2 Variable resistance nonvolatile memory device and programming method for same 有权
标题翻译：可变电阻非易失性存储器件及其编程方法相同
公开(公告)号：US08675387B2
公开(公告)日：2014-03-18
申请号：US13121262
申请日：2010-07-26
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Yoshikazu Katoh
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0002 , G11C13/0069 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： A variable resistance nonvolatile memory device includes a plurality of memory cells in each of which a variable resistance element and a current steering element having two terminals are connected in series. Additionally, a current limit circuit limits a first current flowing in a direction for changing the memory cells to a low resistance state, and a boost circuit increases, when one of the memory cells changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.
摘要翻译：可变电阻非易失性存储器件包括多个存储单元，每个存储单元中的每一个具有两个端子的可变电阻元件和电流控制元件串联连接。此外，电流限制电路限制在用于将存储单元改变为低电阻状态的方向上流动的第一电流，并且当一个存储单元变为低电阻状态时，升压电路增加第一电流在存储单元变为低电阻状态之前的周期。

25. 发明授权

US08472238B2 Variable resistance nonvolatile storage device with oxygen-deficient oxide layer and asymmetric substrate bias effect 有权
标题翻译：具有氧缺陷氧化层的可变电阻非易失性存储器件和不对称衬底偏置效应
公开(公告)号：US08472238B2
公开(公告)日：2013-06-25
申请号：US13534315
申请日：2012-06-27
申请人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
发明人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt
摘要翻译：可变电阻非易失性存储装置包括通过串联连接可变电阻元件（309）形成的存储单元（300），该可变电阻元件（309）包括基于各自具有不同极性的电信号可逆地改变的可变电阻层（309b）和晶体管（307），包括半导体衬底（301）和两个N型扩散层区域（302a，302b），其中可变电阻层（309b）包括过渡金属的氧缺乏氧化物，下电极和上电极（309a， 309c）的材料由下部电极（309a）的标准电极电位V1，上部电极（309c）的标准电极电位V2，过渡金属的标准电极电位Vt满足Vt

26. 发明申请

US20110182109A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD FOR SAME 有权
标题翻译：可变电阻非易失性存储器件及其编程方法
公开(公告)号：US20110182109A1
公开(公告)日：2011-07-28
申请号：US13121262
申请日：2010-07-26
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Yoshikazu Katoh
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Yoshihiko Kanzawa , Shunsaku Muraoka , Yoshikazu Katoh
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0069 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： A variable resistance nonvolatile memory device (100) according to an aspect of the present invention includes: a plurality of memory cells (M11, M12, M21, M22) in each of which a variable resistance element (R11, R12, R21, R22) and a current steering element (D11, D12, D21, D22) having two terminals are connected in series; a current limit circuit (105b) which limits a first current flowing in a direction for changing the memory cells (M11, M12, M21, M22) to a low resistance state; and a boost circuit (105d) which increases, when one of the memory cells (M11, M12, M21, M22) changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.
摘要翻译：根据本发明的一个方面的可变电阻非易失性存储器件（100）包括：多个存储单元（M11，M12，M21，M22），其中可变电阻元件（R11，R12，R21，R22）并且具有两个端子的电流控制元件（D11，D12，D21，D22）串联连接; 电流限制电路（105b），限制在用于将存储单元（M11，M12，M21，M22）改变的方向上流动的第一电流为低电阻状态; 以及升压电路（105d），当存储单元（M11，M12，M21，M22）中的一个变为低电阻状态时，在存储单元变为低电阻状态之前的第一周期内增加第一电流。

27. 发明授权

US08233311B2 Variable resistance nonvolatile storage device having a source line formed of parallel wiring layers connected to each other through vias 有权
标题翻译：可变电阻非易失性存储装置具有通过通孔彼此连接的平行布线形成的源极线
公开(公告)号：US08233311B2
公开(公告)日：2012-07-31
申请号：US13310894
申请日：2011-12-05
申请人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
发明人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt
摘要翻译：可变电阻非易失性存储装置包括通过串联连接可变电阻元件（309）形成的存储单元（300），该可变电阻元件（309）包括基于各自具有不同极性的电信号可逆地改变的可变电阻层（309b）和晶体管（307），包括半导体衬底（301）和两个N型扩散层区域（302a，302b），其中可变电阻层（309b）包括过渡金属的氧缺乏氧化物，下电极和上电极（309a， 309c）的材料由下部电极（309a）的标准电极电位V1，上部电极（309c）的标准电极电位V2，过渡金属的标准电极电位Vt满足Vt

28. 发明授权

US08982603B2 Cross point variable resistance nonvolatile memory device and method of reading thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其读取方法
公开(公告)号：US08982603B2
公开(公告)日：2015-03-17
申请号：US13636169
申请日：2012-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C11/21 , G11C13/00
CPC分类号： G11C11/21 , G11C8/08 , G11C13/00 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/71
摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.
摘要翻译：一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一恒定电流被提供给未选择的字线。

29. 发明授权

US08942050B2 Method of inspecting variable resistance nonvolatile memory device and variable resistance nonvolatile memory device 有权
标题翻译：检查可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US08942050B2
公开(公告)日：2015-01-27
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C7/06 , G11C13/00 , G11C29/50
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

30. 发明申请

US20130223133A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING THEREBY 有权
标题翻译：交叉点可变电阻非易失性存储器件及其写入方法
公开(公告)号：US20130223133A1
公开(公告)日：2013-08-29
申请号：US13883785
申请日：2012-09-06
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C2013/0073 , G11C2013/0088
摘要： A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.
摘要翻译：交叉点可变非易失性存储器件包括存储单元阵列，其包括：具有公共字线的第一存储器单元（例如，存储单元阵列的一部分）; 和第二存储单元（例如，存储单元阵列的另一部分或补偿单元单元）。当通过将预定存储单元改变为第一电阻状态来将第一存储单元中的预定存储单元写入时，字线写入电路向所选字线提供第一电压或第一电流，第一位线写入电路向第一存储器单元的一个位线提供第三电压或第三电流，并且第二位线写入电路将第三电压或第三电流提供给第二存储器单元的A位线或第二行。

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