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21. 发明授权

US06977512B2 Method and apparatus for characterizing shared contacts in high-density SRAM cell design 失效
公开(公告)号：US06977512B2
公开(公告)日：2005-12-20
申请号：US10727719
申请日：2003-12-04
申请人： Franklin Duan , Subramanian Ramesh , Ruggero Castagnetti
发明人： Franklin Duan , Subramanian Ramesh , Ruggero Castagnetti
IPC分类号： G01R27/08 , G01R31/26 , G11C29/02
CPC分类号： G11C29/50008 , G11C11/41 , G11C29/02 , G11C29/022
摘要： Test structures are provided for accurately quantifying shared contact resistance. The test structures are built based upon an actual memory cell, which is self-aligning to allow shared contact chains through an array of test cells. A main array of test cells is built to provide a chain of shared contact resistance. Using the main array of test cells, a resistance in the shared contact chain may be measured. Supplemental arrays of test cells is built to provide a chain of poly side resistance, a chain of island side resistance, a chain of island connection line resistance, and a chain of poly connection resistance. A tester measures resistance using the test structures and uses the values to accurately determine shared contact resistance.

22. 发明授权

US08178909B2 Integrated circuit cell architecture configurable for memory or logic elements 有权
标题翻译：集成电路单元架构可配置为存储器或逻辑元件
公开(公告)号：US08178909B2
公开(公告)日：2012-05-15
申请号：US13242887
申请日：2011-09-23
申请人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
发明人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
IPC分类号： H01L23/528
CPC分类号： H01L27/1104 , G11C8/16 , H01L27/0207 , H01L27/11 , H01L27/11807 , H03K19/1733 , Y10S257/903
摘要： An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
摘要翻译：提供了一种改进的集成电路单元架构，用于存储单元或逻辑元件之间的可配置性。单元架构配置在第一金属层上方的可变层上，其中第一层金属和层保留为固定层。通过将最多两个布局单元耦合在一起，实现单端口或双端口存储单元。同样，通过将单个单元内的晶体管或两个或更多个单元之间的晶体管互连，实现逻辑器件。在每个单元内，位线布置在与字线分开的层上，并且彼此正交延伸。

23. 发明授权

US08166440B1 Basic cell architecture for structured application-specific integrated circuits 失效
标题翻译：用于结构化应用专用集成电路的基本单元架构
公开(公告)号：US08166440B1
公开(公告)日：2012-04-24
申请号：US12139974
申请日：2008-06-16
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
IPC分类号： G06F17/50
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了一种基本单元电路架构，其具有可配置用于形成结构化ASIC内的逻辑器件和/或单/双端口存储器件的固定晶体管的多个单元。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个电池内和/或跨多个电池的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或两者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，并且更完全适用于现代SoC。

24. 发明申请

US20120012896A1 Integrated Circuit Cell Architecture Configurable for Memory or Logic Elements 有权
标题翻译：集成电路单元架构可配置为存储器或逻辑元件
公开(公告)号：US20120012896A1
公开(公告)日：2012-01-19
申请号：US13242887
申请日：2011-09-23
申请人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
发明人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , G11C8/16 , H01L27/0207 , H01L27/11 , H01L27/11807 , H03K19/1733 , Y10S257/903
摘要： An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
摘要翻译：提供了一种改进的集成电路单元架构，用于存储单元或逻辑元件之间的可配置性。单元架构配置在第一金属层上方的可变层上，其中第一层金属和层保留为固定层。通过将最多两个布局单元耦合在一起，实现单端口或双端口存储单元。同样，通过将单个单元内的晶体管或两个或更多个单元之间的晶体管互连，实现逻辑器件。在每个单元内，位线布置在与字线分开的层上，并且彼此正交延伸。

25. 发明授权

US06865614B2 Method for transferring a packed data structure to an unpacked data structure by copying the packed data using pointer 失效
标题翻译：通过使用指针复制打包数据来将打包数据结构传送到未打包的数据结构的方法
公开(公告)号：US06865614B2
公开(公告)日：2005-03-08
申请号：US09897349
申请日：2001-07-02
申请人： Matthew Fischer , Thavatchai Makphaibulchoke , Subramanian Ramesh
发明人： Matthew Fischer , Thavatchai Makphaibulchoke , Subramanian Ramesh
IPC分类号： G06F7/00 , G06F9/00 , G06F9/54 , G06F15/16 , G06F15/163 , G06F17/00
CPC分类号： G06F7/00
摘要： Computer data is transferred from a packed to an unpacked data structure in a computer that enforces aligned memory access and for which the associated compiler lacks a compile-time directive to pack data structures. In an exemplary embodiment, the invention is employed in the pre-processing of Advanced Configuration and Power Interface (ACPI) tables stored in little-endian format for use by a big-endian operating system.
摘要翻译：计算机数据从计算机中的打包数据结构传输到强制对齐内存访问的计算机，并且相关编译器缺少编译时指令来打包数据结构。在示例性实施例中，本发明用于以小端格式存储的高级配置和电源接口（ACPI）表的预处理，以供大端操作系统使用。

26. 发明授权

US08044437B1 Integrated circuit cell architecture configurable for memory or logic elements 有权
标题翻译：集成电路单元架构可配置为存储器或逻辑元件
公开(公告)号：US08044437B1
公开(公告)日：2011-10-25
申请号：US11130350
申请日：2005-05-16
申请人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
发明人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
IPC分类号： H01L27/118
CPC分类号： H01L27/1104 , G11C8/16 , H01L27/0207 , H01L27/11 , H01L27/11807 , H03K19/1733 , Y10S257/903
摘要： An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
摘要翻译：提供了一种改进的集成电路单元架构，用于存储单元或逻辑元件之间的可配置性。单元架构配置在第一金属层上方的可变层上，其中第一层金属和层保留为固定层。通过将最多两个布局单元耦合在一起，实现单端口或双端口存储单元。同样，通过将单个单元内的晶体管或两个或更多个单元之间的晶体管互连，实现逻辑器件。在每个单元内，位线布置在与字线分开的层上，并且彼此正交延伸。

27. 发明授权

US07006369B2 Design and use of a spacer cell to support reconfigurable memories 有权
标题翻译：间隔单元的设计和使用以支持可重构存储器
公开(公告)号：US07006369B2
公开(公告)日：2006-02-28
申请号：US10650192
申请日：2003-08-27
申请人： Ramnath Venkatraman , Rugger Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Rugger Castagnetti , Subramanian Ramesh
IPC分类号： G11C5/06 , G11C11/40
CPC分类号： G11C7/18 , G11C8/16 , H01L27/11 , Y10S257/903
摘要： The present invention provides a method and apparatus for reconfiguring a memory array. Aspects of the present invention include fabricating the memory array as at least one row of single-port cells up to a first metal layer. A split word line having first and second word lines is coupled to the single-port cells in each row, wherein the first word line is patterned in the first metal layer, and the second word line is patterned in a second metal layer. The split word line is further coupled to a spacer cell in the row. The method and apparatus further include programming the memory array into custom configurations based on whether the first and second word lines are connected over the spacer cell, or whether the first and second word lines are left unconnected.
摘要翻译：本发明提供了一种用于重新配置存储器阵列的方法和装置。本发明的方面包括将存储器阵列制造为直到第一金属层的至少一行单端口单元。具有第一和第二字线的分割字线被耦合到每行中的单端口单元，其中第一字线在第一金属层中被图案化，并且第二字线被图案化在第二金属层中。分割字线还耦合到行中的间隔单元。所述方法和装置还包括基于第一和第二字线是否连接在间隔单元上，或者第一和第二字线是否保持不连接，将存储器阵列编程成定制配置。

28. 发明授权

US08429586B2 Basic cell architecture for structured ASICs 失效
标题翻译：结构化ASIC的基本单元架构
公开(公告)号：US08429586B2
公开(公告)日：2013-04-23
申请号：US13424747
申请日：2012-03-20
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl A. Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary S. Delp , Scott A. Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl A. Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary S. Delp , Scott A. Peterson
IPC分类号： G06F17/50
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了具有多个可固定晶体管的单元的基本单元电路架构，其可配置用于形成逻辑器件以及结构化ASIC内的单端口和双端口存储器件。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个单元或多个单元内的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或二者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，更能适应现代的SoC。

29. 发明申请

US20120175683A1 Basic Cell Architecture For Structured ASICs 失效
标题翻译：结构化ASIC的基本单元架构
公开(公告)号：US20120175683A1
公开(公告)日：2012-07-12
申请号：US13424747
申请日：2012-03-20
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
IPC分类号： H01L27/105
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了具有多个可固定晶体管的单元的基本单元电路架构，其可配置用于形成逻辑器件以及结构化ASIC内的单端口和双端口存储器件。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个单元或多个单元内的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或二者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，更能适应现代的SoC。

30. 发明授权

US07114064B2 System and method for accessing an advanced configuration and power interface (ACPI) namespace nodal tree 失效
标题翻译：用于访问高级配置和电源接口（ACPI）命名空间节点树的系统和方法
公开(公告)号：US07114064B2
公开(公告)日：2006-09-26
申请号：US10294888
申请日：2002-11-14
申请人： Subramanian Ramesh , Matthew Fischer
发明人： Subramanian Ramesh , Matthew Fischer
IPC分类号： G06F9/00 , G06F9/24 , G06F15/177
CPC分类号： G06F9/4411 , G06F1/28
摘要： A system and method for accessing an Advanced Configuration and Power Interface (ACPI) namespace nodal tree in a computer platform employing an ACPI-compatible implementation is disclosed.
摘要翻译：公开了一种在采用ACPI兼容实现的计算机平台中访问高级配置和电源接口（ACPI）命名空间节点树的系统和方法。

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