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1. 发明申请

US20050047254A1 Design and use of a spacer cell to support reconfigurable memories 有权
标题翻译：间隔单元的设计和使用以支持可重构存储器
公开(公告)号：US20050047254A1
公开(公告)日：2005-03-03
申请号：US10650192
申请日：2003-08-27
申请人： Ramnath Venkatraman , Rugger Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Rugger Castagnetti , Subramanian Ramesh
IPC分类号： G11C7/18 , G11C8/00 , G11C8/16 , H01L27/11
CPC分类号： G11C7/18 , G11C8/16 , H01L27/11 , Y10S257/903
摘要： A method and apparatus for reconfiguring a memory array is disclosed. Aspects of the present invention include fabricating the memory array as at least one row of single-port cells up to a first metal layer. A split word line having first and second word lines is coupled to the single-port cells in each row, wherein the first word line is patterned in the first metal layer, and the second word line is patterned in a second metal layer. The split word line is further coupled to a spacer cell in the row. The method and apparatus further include programming the base memory array into custom configurations based on whether the first and second word lines are connected over the spacer cell, or whether the first and second word lines are left unconnected.
摘要翻译：公开了一种用于重新配置存储器阵列的方法和装置。本发明的方面包括将存储器阵列制造为直到第一金属层的至少一行单端口单元。具有第一和第二字线的分割字线被耦合到每行中的单端口单元，其中第一字线在第一金属层中被图案化，并且第二字线被图案化在第二金属层中。分割字线还耦合到行中的间隔单元。所述方法和装置还包括基于第一和第二字线是否连接在间隔单元上，或者第一和第二字线是否不连接，将基本存储器阵列编程成定制配置。

2. 发明授权

US07006369B2 Design and use of a spacer cell to support reconfigurable memories 有权
标题翻译：间隔单元的设计和使用以支持可重构存储器
公开(公告)号：US07006369B2
公开(公告)日：2006-02-28
申请号：US10650192
申请日：2003-08-27
申请人： Ramnath Venkatraman , Rugger Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Rugger Castagnetti , Subramanian Ramesh
IPC分类号： G11C5/06 , G11C11/40
CPC分类号： G11C7/18 , G11C8/16 , H01L27/11 , Y10S257/903
摘要： The present invention provides a method and apparatus for reconfiguring a memory array. Aspects of the present invention include fabricating the memory array as at least one row of single-port cells up to a first metal layer. A split word line having first and second word lines is coupled to the single-port cells in each row, wherein the first word line is patterned in the first metal layer, and the second word line is patterned in a second metal layer. The split word line is further coupled to a spacer cell in the row. The method and apparatus further include programming the memory array into custom configurations based on whether the first and second word lines are connected over the spacer cell, or whether the first and second word lines are left unconnected.
摘要翻译：本发明提供了一种用于重新配置存储器阵列的方法和装置。本发明的方面包括将存储器阵列制造为直到第一金属层的至少一行单端口单元。具有第一和第二字线的分割字线被耦合到每行中的单端口单元，其中第一字线在第一金属层中被图案化，并且第二字线被图案化在第二金属层中。分割字线还耦合到行中的间隔单元。所述方法和装置还包括基于第一和第二字线是否连接在间隔单元上，或者第一和第二字线是否保持不连接，将存储器阵列编程成定制配置。

3. 发明授权

US08178909B2 Integrated circuit cell architecture configurable for memory or logic elements 有权
标题翻译：集成电路单元架构可配置为存储器或逻辑元件
公开(公告)号：US08178909B2
公开(公告)日：2012-05-15
申请号：US13242887
申请日：2011-09-23
申请人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
发明人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
IPC分类号： H01L23/528
CPC分类号： H01L27/1104 , G11C8/16 , H01L27/0207 , H01L27/11 , H01L27/11807 , H03K19/1733 , Y10S257/903
摘要： An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
摘要翻译：提供了一种改进的集成电路单元架构，用于存储单元或逻辑元件之间的可配置性。单元架构配置在第一金属层上方的可变层上，其中第一层金属和层保留为固定层。通过将最多两个布局单元耦合在一起，实现单端口或双端口存储单元。同样，通过将单个单元内的晶体管或两个或更多个单元之间的晶体管互连，实现逻辑器件。在每个单元内，位线布置在与字线分开的层上，并且彼此正交延伸。

4. 发明授权

US08166440B1 Basic cell architecture for structured application-specific integrated circuits 失效
标题翻译：用于结构化应用专用集成电路的基本单元架构
公开(公告)号：US08166440B1
公开(公告)日：2012-04-24
申请号：US12139974
申请日：2008-06-16
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
IPC分类号： G06F17/50
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了一种基本单元电路架构，其具有可配置用于形成结构化ASIC内的逻辑器件和/或单/双端口存储器件的固定晶体管的多个单元。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个电池内和/或跨多个电池的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或两者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，并且更完全适用于现代SoC。

5. 发明申请

US20120012896A1 Integrated Circuit Cell Architecture Configurable for Memory or Logic Elements 有权
标题翻译：集成电路单元架构可配置为存储器或逻辑元件
公开(公告)号：US20120012896A1
公开(公告)日：2012-01-19
申请号：US13242887
申请日：2011-09-23
申请人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
发明人： Ramnath Venkatraman , Carl Anthony Monzel, III , Subramanian Ramesh
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , G11C8/16 , H01L27/0207 , H01L27/11 , H01L27/11807 , H03K19/1733 , Y10S257/903
摘要： An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
摘要翻译：提供了一种改进的集成电路单元架构，用于存储单元或逻辑元件之间的可配置性。单元架构配置在第一金属层上方的可变层上，其中第一层金属和层保留为固定层。通过将最多两个布局单元耦合在一起，实现单端口或双端口存储单元。同样，通过将单个单元内的晶体管或两个或更多个单元之间的晶体管互连，实现逻辑器件。在每个单元内，位线布置在与字线分开的层上，并且彼此正交延伸。

6. 发明申请

US20100080035A1 SRAM BASED ONE-TIME-PROGRAMMABLE MEMORY 有权
标题翻译：基于SRAM的一次可编程存储器
公开(公告)号：US20100080035A1
公开(公告)日：2010-04-01
申请号：US12239469
申请日：2008-09-26
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C17/08
CPC分类号： G11C17/16 , G11C17/18
摘要： Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state.
摘要翻译：公开了一种用于提供基于SRAM存储器技术的快速响应一次可编程（OTP）存储器和MOS晶体管的固有击穿特性的方法和装置。 SRAM存储单元电路的每个存储单元连接到编程电路。编程电路由连接到SRAM存储器电路的两个交叉耦合反相器的存储节点（SN和SNB，其中SNB是SN的互补值）的两组MOS晶体管组成。将期望的数据组加载到电路中，然后通过施加并重复地循环编程电路的MOS晶体管的源极和漏极上的“老化”电压并接近特性的ON状态触发电压而被烧录双极结晶体管包含在MOS晶体管内。在重复循环源极至漏极电压之后，编程电路内的目标MOS晶体管在晶体管的栅极，漏极和/或源极之间分解和短路。当系统恢复正常运行时，编程电路将连接到地，Vdd或Vss，SRAM单元电路的两个节点之一将通过编程电路短路到地Vdd或Vss，从而强制保留编程数据状态。

7. 发明授权

US07404154B1 Basic cell architecture for structured application-specific integrated circuits 有权
标题翻译：用于结构化应用专用集成电路的基本单元架构
公开(公告)号：US07404154B1
公开(公告)日：2008-07-22
申请号：US11189026
申请日：2005-07-25
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
IPC分类号： G06F17/50
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了一种基本单元电路架构，其具有可配置用于形成结构化ASIC内的逻辑器件和/或单/双端口存储器件的固定晶体管的多个单元。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个电池内和/或跨多个电池的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或两者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，并且更完全适用于现代SoC。

8. 发明授权

US06934174B2 Reconfigurable memory arrays 有权
标题翻译：可重构内存阵列
公开(公告)号：US06934174B2
公开(公告)日：2005-08-23
申请号：US10655053
申请日：2003-09-03
申请人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
发明人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
IPC分类号： G11C5/02 , G11C7/02 , H01L27/02 , H01L27/105
CPC分类号： G11C5/025 , H01L27/0203 , H01L27/105
摘要： A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.
摘要翻译：公开了一种用于重配置存储器阵列的方法和系统。最初，存储器阵列中的单元以与预定义的层基本上相同的结构进行构图。此后，通过对预定层上的单元进行图案化，使得第一多个单元用作存储单元，并且第二多个单元被图案化为用作存储器阵列的断点的虚拟行或列，来重构存储器阵列。

9. 发明授权

US07869251B2 SRAM based one-time-programmable memory 有权
标题翻译：基于SRAM的一次可编程存储器
公开(公告)号：US07869251B2
公开(公告)日：2011-01-11
申请号：US12239469
申请日：2008-09-26
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state.
摘要翻译：公开了一种用于提供基于SRAM存储器技术的快速响应一次可编程（OTP）存储器和MOS晶体管的固有击穿特性的方法和装置。 SRAM存储单元电路的每个存储单元连接到编程电路。编程电路由连接到SRAM存储器电路的两个交叉耦合反相器的存储节点（SN和SNB，其中SNB是SN的互补值）的两组MOS晶体管组成。将期望的数据组加载到电路中，然后通过施加并重复地循环编程电路的MOS晶体管的源极和漏极上的“老化”电压并接近特性的ON状态触发电压而被烧录双极结晶体管包含在MOS晶体管内。在重复循环源极至漏极电压之后，编程电路内的目标MOS晶体管在晶体管的栅极，漏极和/或源极之间分解和短路。当系统恢复正常运行时，编程电路将连接到地，Vdd或Vss，SRAM单元电路的两个节点之一将通过编程电路短路到地Vdd或Vss，从而强制保留编程数据状态。

10. 发明授权

US07440356B2 Modular design of multiport memory bitcells 有权
标题翻译：多端口存储器单元的模块化设计
公开(公告)号：US07440356B2
公开(公告)日：2008-10-21
申请号：US11487061
申请日：2006-07-13
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C8/00
CPC分类号： H01L27/11 , G11C8/16 , G11C11/412 , H01L27/1104
摘要： The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.
摘要翻译：本发明提供一种用于设计和模块化扩展多端口比特单元的系统和方法。描述了一种模块化设计方法，它降低了设计多端口位单元的复杂性，同时遵循了各种半导体制造提供商的DFM规则。模块化设计可以被解析成诸如读端口模块，写端口模块和可以容易地互连以构建多端口位单元的上拉模块的模块。这些模块还可以独立地定尺寸和组装以实现期望的读取边缘，写入边距，静态噪声容限以及读取访问时间和写入时间。

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