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21. 发明授权

US07719844B2 Stackable self-aligning insulative guide tray for holding semiconductor substrates 有权
标题翻译：用于保持半导体衬底的可堆叠自对准绝缘导板
公开(公告)号：US07719844B2
公开(公告)日：2010-05-18
申请号：US11999747
申请日：2007-12-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： G06F1/16
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A reconfigurable high performance computer includes a stack of self-aligning, injection-molded plastic, insulative guide trays. Each insulative guide tray retains at least one semiconductor substrate assembly (SSA) in a lateral dimension with respect to a set of elastomeric connectors. The trays hold the SSAs and the elastomeric connectors such that the elastomeric connectors are sandwiched between, and interconnect, adjacent semiconductor substrates proceeding down the stack. The trays also hold comb-shaped power bus bar assemblies such that power bus bars contact and supply power to circuitry of the SSAs of the stack.
摘要翻译：可重新配置的高性能计算机包括一堆自对准，注塑塑料，绝缘导向盘。每个绝缘引导托盘相对于一组弹性体连接器在侧向尺寸上保持至少一个半导体衬底组件（SSA）。托盘固定SSA和弹性体连接器，使得弹性体连接器夹在相邻的半导体衬底之间并互连在堆叠之上。托盘还保持梳状电力汇流条组件，使得电力母线与电池堆的SSA的电路接触并供电。

22. 发明授权

US07667473B1 Flip-chip package having thermal expansion posts 有权
标题翻译：具有热膨胀柱的倒装芯片封装
公开(公告)号：US07667473B1
公开(公告)日：2010-02-23
申请号：US11238419
申请日：2005-09-28
申请人： Robert O. Conn , Steven J. Carey
发明人： Robert O. Conn , Steven J. Carey
IPC分类号： G01R31/02
CPC分类号： H01L23/10 , H01L21/563 , H01L23/3128 , H01L23/3675 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/0554 , H01L2224/05572 , H01L2224/05573 , H01L2224/10175 , H01L2224/13016 , H01L2224/131 , H01L2224/13147 , H01L2224/16057 , H01L2224/16225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81193 , H01L2224/81385 , H01L2224/814 , H01L2224/81447 , H01L2224/81815 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19041 , H01L2924/014 , H01L2924/01014 , H01L2924/00 , H01L2924/3512 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package having a substrate and a die includes a plurality of conductive posts attached to the substrate and bonded to an active surface of the die via a plurality of corresponding microbumps. The conductive posts are flexible and extend beyond the top surface of the substrate a sufficient distance to absorb lateral forces exerted upon the microbumps.
摘要翻译：具有基板和模具的半导体封装包括附接到基板的多个导电柱，并且经由多个相应的微凸块结合到模具的有效表面。导电柱是柔性的并且延伸超过基板的顶表面足够的距离以吸收施加在微胶片上的横向力。

23. 发明申请

US20090267183A1 Through-substrate power-conducting via with embedded capacitance 审中-公开
标题翻译：具有嵌入式电容的通过衬底的导电通孔
公开(公告)号：US20090267183A1
公开(公告)日：2009-10-29
申请号：US12150529
申请日：2008-04-28
申请人： Dorota Temple , Robert O. Conn
发明人： Dorota Temple , Robert O. Conn
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/481 , H01L21/76898 , H01L2224/05568 , H01L2224/05573 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/014 , H01L2224/05599
摘要： When integrated circuits are mounted on a substrate, little space is often available for the required large number of bypass capacitors. A novel substrate structure therefore includes many closely spaced through-holes that extend from a first surface of the substrate to a second surface of the substrate. Each through-hole includes a first conducting layer, a dielectric layer, and a second conducting layer. The first and second conducting layers and the intervening dielectric layer constitute a via having a substantial capacitance (one picofarad). Some of the many vias provide bypass capacitance directly under the integrated circuits. A first set of vias supplies power from a power bus bar on one side of the substrate to the integrated circuits on the other side. A second set of vias sinks current from the integrated circuits on the other side, through the substrate, and to a ground bus bar on the one side.
摘要翻译：当集成电路安装在基板上时，通常对所需的大量旁路电容器几乎没有空间。因此，新颖的衬底结构包括从衬底的第一表面延伸到衬底的第二表面的许多紧密间隔的通孔。每个通孔包括第一导电层，电介质层和第二导电层。第一和第二导电层和介入介电层构成具有相当大电容（一个皮法）的通孔。许多通孔中的一些直接在集成电路下提供旁路电容。第一组通孔从基板一侧的电源母线供给另一侧的集成电路。第二组通孔从另一侧的集成电路，通过基板和一侧的接地母线吸收电流。

24. 发明申请

US20090080152A1 Stackable self-aligning insulative guide tray for holding semiconductor substrates 有权
标题翻译：用于保持半导体衬底的可堆叠自对准绝缘导板
公开(公告)号：US20090080152A1
公开(公告)日：2009-03-26
申请号：US11999747
申请日：2007-12-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H05K7/02 , H05K7/20 , A47B81/00 , H05K7/00
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A reconfigurable high performance computer includes a stack of self-aligning, injection-molded plastic, insulative guide trays. Each insulative guide tray retains at least one semiconductor substrate assembly (SSA) in a lateral dimension with respect to a set of elastomeric connectors. The trays hold the SSAs and the elastomeric connectors such that the elastomeric connectors are sandwiched between, and interconnect, adjacent semiconductor substrates proceeding down the stack. The trays also hold comb-shaped power bus bar assemblies such that power bus bars contact and supply power to circuitry of the SSAs of the stack.
摘要翻译：可重新配置的高性能计算机包括一堆自对准，注塑塑料，绝缘导向盘。每个绝缘引导托盘相对于一组弹性体连接器在侧向尺寸上保持至少一个半导体衬底组件（SSA）。托盘固定SSA和弹性体连接器，使得弹性体连接器夹在相邻的半导体衬底之间并互连在堆叠之上。托盘还保持梳状电力汇流条组件，使得电力母线与电池堆的SSA的电路接触并供电。

25. 发明授权

US07233061B1 Interposer for impedance matching 有权
标题翻译：用于阻抗匹配的插入器
公开(公告)号：US07233061B1
公开(公告)日：2007-06-19
申请号：US10698906
申请日：2003-10-31
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/02
CPC分类号： H01L23/50 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/66 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/16265 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/81143 , H01L2224/8121 , H01L2224/81815 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/09701 , H01L2924/10253 , H01L2924/12036 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/19011 , H01L2924/19041 , H01L2924/19103 , H01L2924/30107 , H01L2924/3011 , H05K1/0231 , H05K1/0237 , H05K1/141 , H05K1/142 , H05K1/162 , H05K3/3436 , H05K2201/09309 , H05K2201/10378 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.
摘要翻译：电容插入器（caposer）设置在芯片与封装的内表面之间的集成电路封装内。钳口内的导电层构成旁路电容器。在通孔捕获器中，裸片上的微型凸块通过钳口中的通孔并与封装上相应的着陆焊盘接触。当电容和接地微型突起通过电容器时，接触旁路电容器的电极。在通孔容量中，芯片上的电源和接地微型突起通过电源和接地通孔耦合到封装上的电源和接地焊盘以及旁路电容器的板上，延伸通过钳口。在信号再分配电容器中，钳位器内的导体在管芯微突起和封装着陆焊盘之间重新分配信号。在阻抗匹配钳位器中，钳位器内的端接结构为印刷电路板迹线提供阻抗匹配。

26. 发明授权

US06945712B1 Fiber optic field programmable gate array integrated circuit packaging 有权
标题翻译：光纤现场可编程门阵列集成电路封装
公开(公告)号：US06945712B1
公开(公告)日：2005-09-20
申请号：US10376915
申请日：2003-02-27
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： G02B6/38 , G02B6/42 , G02B6/43
CPC分类号： G02B6/4214 , G02B6/3897 , G02B6/4246 , G02B6/4292 , G02B6/43 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： An FPGA is readily connectable to a high-speed fiber optic link by snap fitting an external fiber optic cable into an accommodating duplex fiber optic connector of a low-profile packaged FPGA integrated circuit. The low-profile packaged FPGA integrated circuit includes a die-bonded assembly disposed within a co-fired multilayer ceramic integrated circuit package. The die-bonded assembly includes the optoelectronic die, the bottom surface of which is die-bonded and electrically interconnected by micropads to the upper surface of the core of an FPGA integrated circuit die. A first optical fiber communicates light from the connector, through the package, and to a photodetector on the optoelectronic die. A second optical fiber communicates light from a laser diode on the optoelectronic die, through the package, and to the connector. In some embodiments, a micromirror device is disposed within the package to redirect light between the optoelectronic die and the optical fibers.
摘要翻译：通过将外部光纤电缆卡扣配合到低调封装的FPGA集成电路的容纳双工光纤连接器中，FPGA可以容易地连接到高速光纤链路。薄型封装的FPGA集成电路包括设置在共烧多层陶瓷集成电路封装内的芯片结合组件。芯片接合组件包括光电裸片，其底表面被芯片键合并且通过微型电子电互连到FPGA集成电路芯片的芯的上表面。第一光纤将来自连接器的光，通过封装传送到光电管芯上的光电检测器。第二光纤将来自光电裸片上的激光二极管的光，通过封装和连接器通信。在一些实施例中，微反射镜装置设置在封装内以在光电管芯和光纤之间重定向光。

27. 发明授权

US6150863A User-controlled delay circuit for a programmable logic device 失效
标题翻译：可编程逻辑器件的用户控制延迟电路
公开(公告)号：US6150863A
公开(公告)日：2000-11-21
申请号：US53879
申请日：1998-04-01
申请人： Robert O. Conn , Peter H. Alfke
发明人： Robert O. Conn , Peter H. Alfke
IPC分类号： H03K5/00 , H03K5/13 , H03H11/26
CPC分类号： H03K5/133 , H03K2005/00104
摘要： An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.
摘要翻译：提供了包括用户控制的可变延迟输入电路的输入块。输入电路适于接收输入信号并在输出节点上输出输入信号的延迟版本。多个控制信号指示施加在输入信号上的延迟量。使用控制信号发生器建立控制信号，并因此建立延迟量。发电机可用于主动改变延迟。在一个实施例中，控制信号发生器被实现为将延迟电路的延迟周期与分布式时钟信号的延迟周期自动匹配的反馈电路。

28. 发明授权

US5852323A Electrically programmable antifuse using metal penetration of a P-N junction 失效
标题翻译：使用金属穿透P-N结的电可编程反熔丝
公开(公告)号：US5852323A
公开(公告)日：1998-12-22
申请号：US784226
申请日：1997-01-16
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011
摘要： An antifuse is described that can be formed without masks or mask steps beyond those required for a conventional CMOS process. The antifuse includes adjacent p-type and n-type diffusion regions that together form a P-N junction. The diffusion regions are tapered toward one another such that the P-N junction is located at a necked-down region of the antifuse. The diffusion regions are connected to respective terminals of a programming-voltage source via first and second metal electrical contacts, typically of aluminum metal. Each of the first and second electrical contacts includes a point directed toward the other of the first and second electrical contacts. The antifuse is programmed by providing a reverse-bias programming voltage across the electrical contacts. This programming voltage exceeds the breakdown voltage of the P-N junction so that current flows through the necked-down region of the antifuse between the points on the respective first and second electrical contacts. This current heats the region between the opposite points to create a hot filament between the first and second metal contacts. Metal from the metal contacts then diffuses along the filament to form a conductor between metal contacts.
摘要翻译：描述了可以在没有常规CMOS工艺所需的掩模或掩模步骤的情况下形成反熔丝。反熔丝包括一起形成P-N结的相邻的p型和n型扩散区。扩散区域朝向彼此逐渐变细，使得P-N结位于反熔丝的颈缩区域。扩散区域通过第一和第二金属电触点（通常为铝金属）连接到编程电压源的相应端子。第一和第二电触头中的每一个包括指向第一和第二电触头中的另一个的点。通过在电触点上提供反向偏置编程电压来编程反熔丝。该编程电压超过P-N结的击穿电压，使得电流流过相应的第一和第二电触点之间的点之间的反熔丝的颈缩区域。该电流加热相对点之间的区域，以在第一和第二金属触点之间产生热丝。来自金属接触件的金属然后沿着细丝扩散以在金属触点之间形成导体。

29. 发明授权

US5789938A Structure and method for reading blocks of data from selectable points in a memory device 失效
公开(公告)号：US5789938A
公开(公告)日：1998-08-04
申请号：US707545
申请日：1996-09-04
申请人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
发明人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
IPC分类号： G11C8/04 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17772 , G11C8/04 , H03K19/1776
摘要： A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.

30. 发明授权

US08671560B2 In system reflow of low temperature eutectic bond balls 失效
标题翻译：在低温共晶粘结球的系统回流中
公开(公告)号：US08671560B2
公开(公告)日：2014-03-18
申请号：US12798132
申请日：2010-03-30
申请人： Robert O. Conn , Daniel S. Stevenson
发明人： Robert O. Conn , Daniel S. Stevenson
IPC分类号： H05K3/20
CPC分类号： H01L24/81 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0655 , H01L2224/05147 , H01L2224/10135 , H01L2224/10165 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13562 , H01L2224/13655 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/8114 , H01L2224/81141 , H01L2224/81191 , H01L2224/81234 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H05K3/3436 , H05K3/3494 , H05K2203/047 , H05K2203/163 , Y02P70/613 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49169 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.
摘要翻译：低温焊球连接两个具有不同的线性热膨胀系数的结构。制造集成电路以加热该器件，使得低温接合球熔化。熔化后，粘结球固化，并且使粘合球固化的装置进行操作。在一个示例中，两个结构之一是半导体衬底，而另一个结构是印刷电路板。集成电路是安装到半导体衬底的裸片。结合球包括至少5％的铟，并且集成电路是装载有位流的FPGA。位流配置FPGA，使得FPGA具有增加的功率耗散，其熔化了球。熔化后，将第二位流装载到FPGA中，并使用第二位流以正常用户模式操作FPGA。

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